Here are the screens of the new software furnished with the CT60 !
CT60 Project Historical
March 2005
New ABE 5M for CT60 :
Modification of I6 locking from the CT bus slot. This bug was discovered by the developers of the EtherNAT card. The I6 was blocking the INT6 from F30 motherboard (MFP & DSP).
The 5M is successor of 5L. The 5K (F30 16 MHz only bus) is no more supported.
To use a daughter card on CT60, the ABE 5M MUST be used. This update is not needed for CT63 !
November 6th 2003
New SDR 5E : solve the SPURIOUS INT (error #24) problem occuring with some 060. This problem may occur indirectly as a BUS ERROR or an ACCESS FAULT.
October 1st 2003
Test of the last mask of 68060 : 1E41J - Rev6 - 1999
The CT60 run at 100 MHz !
147 MIPS & 104 MB/s with SDRAM !
August 2003
New ABE (5K & 5L) :
- Modification of the UDS & LDS generator for readings to correct a bug that was discovered with HD Driver 8.13. This bug can appear with some other software ! Update your ABE !
July 2003
New ABE (5I & 5J) :
- Modification of the BUS ERROR from the Falcon for the ECLIPSE board.
- New Data Latch to solve timing problems with some IDE HDD and some motherboards and with some Falcon daughter cards like Eclipse too.
- New Watch Dog timer done with the new 15.36us clock from SDR (new refresh). NEED TO CUT A TRACE ON ALL CT60 !
- Modification of the Falcon DTACK sampling to solve a problem of reading (sometimes) the MFP & SDMA registers !
- There are now two version of ABE :
- First letter (ie 5I) is for the standard CT60 running the F30 bus at 16 & 20 MHz.
- Second letter (ie 5J) is for CT60 running the F30 bus at 25 MHz (40 MHz OSC replaced by a 50 MHz). The ST-RAM Read accesses are done by 5 cycles instead of 4. Works too on 16 & 20 MHz bus.
New SDR (5D) :
- The RESET OUT signal (reset instruction) is no more supported to avoid a hardware dead lock at power on.
- 2 pages each of 8 or 16 KB (depending of the chips on the DIMM).
- Write access with 3-1-1-1 and Read access with 5-1-1-1 cycles to increase the marge with higher temperature and more heavy loading of the 060 ADD bus if connecting a future daughter board on the 060 slot.
- NEW REFRESH Master clock (66.66 MHz) to refresh every 15.36 us or 7.68 us (depending of the chips on the DIMM). NEED TO CUT A TRACE ON ALL CT60 !
June 2003
New data latch into ABE (4H) to solve timing problems with 25 MHz F30 bus.
New SDR (4F) :
- interleaving of the two 32-bit physical banks of the DIMM : --> hit page size x 2 !
- second address register to open simultaneously 2 pages at different addresses : --> + 5 MB/s !
Remove a timing bug at 20/25 MHz on the bus arbiter (ABE).
Tests at 66/16 with and without the Atari clock patch (74F08).
Tests and debug at 66/16, 66/20 & 66/25 MHz for SDMA clock and SDMA data transfers as master.
Typing of the installation documentations and photos.
Shipping of the first units for developers.
May 2003
Bus arbiter (into ABE60) modified to solve two consecutive bugs : Blitter & SDMA run fine at 66 & 72 MHz (ABE version = 4B)
General tests at 66/16 MHz & 66/20 MHz (speed of CT60 / speed of F30 bus).
Test of the 060 (model 60 MHz) at 72 MHz : no more supported.
ST-Ram Write accesses increased by 25% (3 clock cycles instead of 4 ) !
Optimization of SDR60 :
- Remove 1 clock cycle on Page Miss accesses and adding the capacity for the 512 MB DIMM (256 on each side).
- Remove 1 clock cycle on page HIT accesses : 4-1-1-1 for Reads & 2-1-1-1 for Writes.
April 2003
Buying a 200MHz/16chanels logical analyser ! Picture of the CT60 + analyser (69KB)
The last bug found on SDR60 : run fine with the page mode ! SDR60 version = 1. The transfers rate are lower than the theorical ones and it is clear that the 060 is spending some time between each burst with SDRAM. So, we touch now the limit of the 060...SDRAM bandwidth will never be 100% used.
The DSP bug is solved : run fine !
The problems with SCC and interupts are solved.
December 2002
An other bug found on SDR60, but the SINGLE accesses have yet a problem.
It stills a problem of timing when reading the Host of the DSP and the INT vector of the SCC. This problem is immediat when boosting the falcon motherboard to 20MHz.
June 2002
A bug found on SDR60. A bug on DSP transfers not yet found.
CT60/F030 Bus arbiter is near finished.
April 2nd 2002
Manufacturing of the board.
February 13rd 2002
The CT60 runs at 66 & 80 MHz and the SDRAM controller is running at 66 and 80 MHz.
The CT60 runs at 100 MHz but the 060 crashed as soon as we activate the internal CACHES because of internal timing problems... The SDR60 controller doesn't run correctly at 100 MHz...
The 060 CPU labelled '50 MHz' crash at 80 MHz with the activated caches ! Here is the Amiga world 060 limit of 72 MHz !
I so decided to furnish the CT60 cards with a socketed Oscillator that will be a 66.66 MHz for CT60 with a 060 labelled '50' and a 80 MHz for the CT60 with a 060 labelled '60'. It's the user free decision to try to boost with a higher value oscillator (if he finds it !).
The CT60 will be furnished with a Heatsink + Fan bloc (a Pentium I model) not noisly, necessary for a good running of the 060.
The IDE LED of the towers is now connectable without solders on the CT60...
January 8th 2002
The 060 runs at 66 MHz & 80 MHz (the model is a 60 MHz) and correctly accesses to the Falcon mainboard running at 16 MHz : the videl is correctly set.
December 27th 2001
The 060 boots.
November 29th 2001
Assembly of the board for production validation : prototype.jpg (98KB).
November 18th 2001
Manual routing of the board is finished. Shematics were modified (see below).
September 15th 2001
Schematics are finished.
August 3rd 2001
The logic design of RR-J is finished and I was able to work again on CT60. The work's summary :
- brainstorming on ABE-60.
- modification of the 030 to Flash accesses (ABE-60).
- several attempts to place & lock the data & add signals on the pins of the ABE chip to facilitate the PCB routing.
March 7th 2001
The BIOS for the CT60 boot is ready !
The design of the logic is ready since February.
The chip ABE-60 was optimised and the SDR-60 (SDRAM controller) seems to be nice...
The data transfers performances are the ones that are on my web pages...They were calculated with the SDR60 capacities and the MOVE.L instruction execution time of the 060.
So,
A BURST READ/WRITE into an OPENED PAGE (HIT) gives :
- 8 / 7 cycles ---> 128 / 146 MBytes/s at 64 MHz !
A BURST READ/WRITE into a new page (MISS) gives :
-13 / 11 cycles ---> 79 / 93 MBytes/s at 64 MHz !
This last test assumes that each access is into a new page (CPU jumps over the page frontier).
This test is commonly called 'RANDOM ACCESS'.
Pages sizes are from 4 to 16 KBytes depending of the SDRAM DIMM capacity & model (see the table of 'SDRAM').
The next phase will be the ROUTING of the board...
Unfortunately, I have no more time to do that and it will not done before April....
My principle job since beginning of January is RIORED-J and it has the biggest priority in a market (and financial) point of view...
Next (good) news will be in April...
December 00
Wonderfull ! The CT60 will be able to furnish you the CPU temperature !
How is it possible ? The 060 processor has two not known (because not on the 040 !) pins THERM0 & THERM1.
These pins are connected to the CORE thermical resistor and can be connected to a small Analog/Digital 8-Bit converter...
Boost the 060 without danger : the software read the temperature with a 2.8° C precision and gives you an ALARM at all moment (multitasking compatible) !
Here are the screens of the new software furnished with the CT60 !
