CTHG (CT60 + CTPCI Hardware Guide) - Last update : January 2012
F030 HARWARE REGISTERS - Last update : March 2009
Patch for MonTT (the Devpac debugger) on 060
SCHEMATICS : CT63_Schematics.pdf (919 KB)
PCB LOW RESOLUTION (GIF) : PCBeagle_LR (112 KB)
PCB HIGH RESOLUTION (GIF) : PCBeagle_HR (313 KB)
Logical Analyser connected on the CT60 : Analyse.jpg (69KB) , AnalyseDSP.jpg (70KB)
Bus Arbitration Block Diagram : CT60_Arbi.jpg (27KB)
Bus Dynamic Adapter : ABE-DataConv.jpg (20KB)
68060 Product Brief : Download TXT file (PDF file version at Motorola)
060 EVOLUTION
OCT 1996 XC MASKS (F43G, G65V, G59Y, E41J) ERRATA 4.0 : Download PDF file
FEB 1999 MC E41J MASK : Download HTML file
ARCHITECTURE
DESIGN CHRONOGRAMS
Falcon Accesses : ABE-F30Access.jpg (54KB)
Flash 16-bits WRITE Accesses : ABE-FLASHW.jpg (24KB)
Flash 32-bits READ Accesses : ABE-FLASH.jpg (37KB)
Flash 16-bits Accesses from 68030 : ABE-FLASH030.jpg (30KB)
SDRAM Refresh : SDR-Refresh.jpg (35KB)
SDRAM BURST with Page Hit : SDR-BurstHIT.jpg (50KB)
SDRAM BURST with Page Miss : SDR-BurstMISS.jpg (53KB)
SDRAM SINGLE READ with Page Hit : SDR-SingleHITR.jpg (66KB)
SDRAM SINGLE WRITE with Page Hit : SDR-SingleHITW.jpg (66KB)
LOGIC ANALYSE (200 MHz) CHRONOGRAMS
Arbiter Boot
CME = CT60 Master Enable
Arbiter - Bus mastering from CT60 to F030
HIGHZ = High Impedance of the F030 GALs outputs --> Master on the EXP slot
Arbiter - Bus mastering from F030 to CT60
Button Reset
Power Up Reset
ST-Ram Read & Write accesses at 16 MHz
Blitter master on bus at 16 MHz
SDMA Read at 16 MHz
SDMA Read at 25 MHz
DSP(32MHz) INT Vector ACK
MFP (16MHz bus) INT Vector ACK
F030 Boot (mode 68030)
F030 Blitter (mode 68030)
