cpldfit:  version J.36                              Xilinx Inc.
                                  Fitter Report
Design Name: CTPCI_1N                            Date: 11- 1-2012,  1:17PM
Device Used: XC95288XL-7-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
277/288 ( 96%) 792 /1440 ( 55%) 665/864 ( 77%)   247/288 ( 86%) 113/117 ( 97%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          18/18*      39/54       40/90       7/ 8
FB2          18/18*      44/54       60/90       8/10
FB3          18/18*      38/54       36/90       2/ 5
FB4          18/18*      44/54       54/90       6/ 6*
FB5          18/18*      41/54       44/90       6/ 8
FB6          18/18*      44/54       51/90       6/ 8
FB7          18/18*      43/54       53/90       1/ 4
FB8          18/18*      38/54       51/90       5/ 5*
FB9          15/18       31/54       22/90       2/ 9
FB10         14/18       44/54       54/90       9/10
FB11         18/18*      44/54       55/90       6/ 7
FB12         15/18       44/54       51/90       6/ 6*
FB13         18/18*      42/54       60/90       6/ 6*
FB14         18/18*      43/54       52/90       4/ 8
FB15         18/18*      43/54       53/90       8/ 9
FB16         17/18       43/54       56/90       4/ 8
             -----       -----       -----      -----    
            277/288     665/864     792/1440    86/117

* - Resource is exhausted

** Global Control Resources **

Signal 'clk' mapped onto global clock net GCK1.
Signal 'pciclk' mapped onto global clock net GCK2.
Signal 'pclk' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Signal 'rst' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   24          24    |  I/O              :   105     109
Output        :   22          22    |  GCK/IO           :     3       3
Bidirectional :   63          63    |  GTS/IO           :     4       4
GCK           :    3           3    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total    113         113

** Power Data **

There are 277 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

INFO:Cpld:994 - Exhaustive fitting is trying pterm limit: 25 and input limit: 54
*************************  Summary of Mapped Logic  ************************

** 86 Outputs **

Signal                          Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                            Pts   Inps          No.  Type    Use     Mode Rate State
tt1                             1     1     FB1_5   20   I/O     I/O     STD  FAST 
tt0                             1     1     FB1_6   21   I/O     I/O     STD  FAST 
tm2                             1     1     FB1_8   22   I/O     I/O     STD  FAST 
tm1                             1     1     FB1_10  23   I/O     I/O     STD  FAST 
tm0                             1     1     FB1_12  24   I/O     I/O     STD  FAST 
ieo                             4     8     FB1_14  25   I/O     O       STD  FAST RESET
br60                            2     3     FB1_15  26   I/O     O       STD  FAST RESET
tap                             4     5     FB2_2   9    I/O     I/O     STD  FAST RESET
tsp                             3     4     FB2_3   10   I/O     I/O     STD  FAST RESET
burst                           2     4     FB2_5   11   I/O     O       STD  FAST 
ct_irq                          5     9     FB2_10  14   I/O     O       STD  FAST 
bs3                             4     5     FB2_12  15   I/O     I/O     STD  FAST 
bs2                             4     5     FB2_14  16   I/O     O       STD  FAST 
bs1                             3     5     FB2_15  17   I/O     I/O     STD  FAST 
bs0                             2     3     FB2_17  19   I/O     O       STD  FAST 
bgslt                           1     3     FB3_12  31   I/O     O       STD  FAST RESET
ts6                             2     3     FB3_15  33   I/O     I/O     STD  FAST RESET
d0                              4     10    FB4_2   2    GTS/I/O I/O     STD  FAST RESET
d1                              4     10    FB4_5   3    GTS/I/O I/O     STD  FAST RESET
d2                              4     10    FB4_6   4    I/O     I/O     STD  FAST RESET
d3                              4     10    FB4_8   5    GTS/I/O I/O     STD  FAST RESET
d4                              4     10    FB4_12  6    GTS/I/O I/O     STD  FAST RESET
bi                              1     1     FB4_14  7    I/O     O       STD  FAST 
pclk                            0     0     FB5_8   38   GCK/I/O GCK/O   STD  FAST RESET
tsiz1                           2     4     FB5_10  39   I/O     I/O     STD  FAST 
tsiz0                           2     4     FB5_12  40   I/O     I/O     STD  FAST 
siz1                            2     3     FB5_14  41   I/O     I/O     STD  FAST 
bdip                            5     8     FB5_15  43   I/O     O       STD  FAST RESET
siz0                            2     3     FB5_17  44   I/O     I/O     STD  FAST 
teap                            2     3     FB6_2   135  I/O     O       STD  FAST RESET
bgplx                           1     2     FB6_3   136  I/O     O       STD  FAST RESET
d8                              3     7     FB6_5   137  I/O     I/O     STD  FAST RESET
d7                              4     10    FB6_8   139  I/O     I/O     STD  FAST RESET
d6                              4     10    FB6_10  140  I/O     I/O     STD  FAST RESET
d5                              4     10    FB6_14  142  I/O     I/O     STD  FAST RESET
ta6                             5     11    FB7_5   46   I/O     I/O     STD  FAST RESET
d13                             3     7     FB8_2   130  I/O     I/O     STD  FAST RESET
d12                             3     7     FB8_3   131  I/O     I/O     STD  FAST RESET
d11                             3     7     FB8_5   132  I/O     I/O     STD  FAST RESET
d10                             3     7     FB8_8   133  I/O     I/O     STD  FAST RESET

Signal                          Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                            Pts   Inps          No.  Type    Use     Mode Rate State
d9                              3     7     FB8_10  134  I/O     I/O     STD  FAST RESET
cs1                             1     2     FB9_14  58   I/O     O       STD  FAST 
cs0                             1     2     FB9_17  59   I/O     O       STD  FAST 
d22                             5     13    FB10_2  117  I/O     I/O     STD  FAST RESET
d21                             4     10    FB10_3  118  I/O     I/O     STD  FAST RESET
d20                             5     13    FB10_5  119  I/O     I/O     STD  FAST RESET
d19                             5     13    FB10_6  120  I/O     I/O     STD  FAST RESET
d18                             5     13    FB10_8  121  I/O     I/O     STD  FAST RESET
d17                             5     13    FB10_10 124  I/O     I/O     STD  FAST RESET
d16                             5     13    FB10_11 125  I/O     I/O     STD  FAST RESET
d15                             3     7     FB10_12 126  I/O     I/O     STD  FAST RESET
d14                             3     7     FB10_17 129  I/O     I/O     STD  FAST RESET
ior                             2     7     FB11_5  61   I/O     O       STD  FAST RESET
iow                             2     7     FB11_10 64   I/O     O       STD  FAST RESET
id15                            4     7     FB11_11 66   I/O     I/O     STD  FAST RESET
id0                             4     7     FB11_12 68   I/O     I/O     STD  FAST RESET
id14                            4     7     FB11_14 69   I/O     I/O     STD  FAST RESET
id1                             4     7     FB11_17 70   I/O     I/O     STD  FAST RESET
d28                             5     13    FB12_2  110  I/O     I/O     STD  FAST RESET
d27                             5     13    FB12_3  111  I/O     I/O     STD  FAST RESET
d26                             5     13    FB12_5  112  I/O     I/O     STD  FAST RESET
d25                             5     13    FB12_8  113  I/O     I/O     STD  FAST RESET
d24                             4     10    FB12_10 115  I/O     I/O     STD  FAST RESET
d23                             5     13    FB12_12 116  I/O     I/O     STD  FAST RESET
id13                            4     7     FB13_2  71   I/O     I/O     STD  FAST RESET
id2                             4     7     FB13_8  74   I/O     I/O     STD  FAST RESET
id12                            4     7     FB13_11 75   I/O     I/O     STD  FAST RESET
id3                             4     7     FB13_14 76   I/O     I/O     STD  FAST RESET
id11                            4     7     FB13_15 77   I/O     I/O     STD  FAST RESET
id4                             4     7     FB13_17 78   I/O     I/O     STD  FAST RESET
pcirst                          1     2     FB14_3  100  I/O     O       STD  FAST 
d31                             4     10    FB14_11 105  I/O     I/O     STD  FAST RESET
d30                             4     10    FB14_14 106  I/O     I/O     STD  FAST RESET
d29                             4     10    FB14_15 107  I/O     I/O     STD  FAST RESET
id10                            4     7     FB15_2  79   I/O     I/O     STD  FAST RESET
id5                             4     7     FB15_3  80   I/O     I/O     STD  FAST RESET
id9                             4     7     FB15_8  81   I/O     I/O     STD  FAST RESET
id6                             4     7     FB15_10 82   I/O     I/O     STD  FAST RESET
id8                             4     7     FB15_11 83   I/O     I/O     STD  FAST RESET
id7                             4     7     FB15_12 85   I/O     I/O     STD  FAST RESET

Signal                          Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                            Pts   Inps          No.  Type    Use     Mode Rate State
ccs                             1     5     FB15_14 86   I/O     O       STD  FAST 
g0                              7     11    FB15_15 87   I/O     O       STD  FAST RESET
g4                              6     11    FB16_5  93   I/O     O       STD  FAST RESET
g3                              6     11    FB16_6  94   I/O     O       STD  FAST RESET
g2                              6     11    FB16_8  95   I/O     O       STD  FAST RESET
g1                              6     11    FB16_11 97   I/O     O       STD  FAST RESET

** 191 Buried Nodes **

Signal                          Total Total Loc     Pwr  Reg Init
Name                            Pts   Inps          Mode State
ts6c                            1     6     FB1_1   STD  RESET
tapcc0                          1     5     FB1_2   STD  RESET
ta6cc0                          2     6     FB1_3   STD  RESET
stplx                           2     7     FB1_4   STD  RESET
enbi4                           2     7     FB1_7   STD  RESET
enbi3                           2     7     FB1_9   STD  RESET
enbi2                           2     7     FB1_11  STD  RESET
enbi1                           2     7     FB1_13  STD  RESET
ta6cc1                          3     7     FB1_16  STD  RESET
bmplx                           4     9     FB1_17  STD  RESET
ts6p                            8     13    FB1_18  STD  RESET
b4d0                            2     11    FB2_1   STD  RESET
b3d1                            3     13    FB2_4   STD  RESET
b3d0                            3     13    FB2_6   STD  RESET
b2d1                            3     13    FB2_7   STD  RESET
b2d0                            3     13    FB2_8   STD  RESET
b1d0                            3     12    FB2_9   STD  RESET
vect7                           4     9     FB2_11  STD  RESET
vect6                           4     9     FB2_13  STD  RESET
vect5                           4     9     FB2_16  STD  RESET
vect4                           4     9     FB2_18  STD  RESET
psync                           1     5     FB3_1   STD  RESET
peot                            1     5     FB3_2   STD  RESET
tscnt                           2     3     FB3_3   STD  RESET
shift                           2     6     FB3_4   STD  RESET
pcc1                            2     5     FB3_5   STD  RESET
pcc0                            2     7     FB3_6   STD  RESET
b4d7                            2     11    FB3_7   STD  RESET
b4d4                            2     11    FB3_8   STD  RESET
b4d30                           2     11    FB3_9   STD  RESET
b4d3                            2     11    FB3_10  STD  RESET
b4d28                           2     11    FB3_11  STD  RESET
b4d27                           2     11    FB3_13  STD  RESET
b4d1                            2     11    FB3_14  STD  RESET
pcc2                            3     7     FB3_16  STD  RESET
b1d7                            3     12    FB3_17  STD  RESET
b1d30                           3     12    FB3_18  STD  RESET
b4d2                            2     11    FB4_1   STD  RESET
b4d13                           2     11    FB4_3   STD  RESET
b4d12                           2     11    FB4_4   STD  RESET

Signal                          Total Total Loc     Pwr  Reg Init
Name                            Pts   Inps          Mode State
b3d2                            3     13    FB4_7   STD  RESET
b3d13                           3     13    FB4_9   STD  RESET
b3d12                           3     13    FB4_10  STD  RESET
b2d2                            3     13    FB4_11  STD  RESET
b2d13                           3     13    FB4_13  STD  RESET
b2d12                           3     13    FB4_15  STD  RESET
b1d2                            3     12    FB4_16  STD  RESET
b1d12                           3     12    FB4_17  STD  RESET
b1d1                            3     12    FB4_18  STD  RESET
rcs                             1     5     FB5_1   STD  
tapcc1                          2     6     FB5_2   STD  RESET
plx                             2     4     FB5_3   STD  RESET
b4d6                            2     11    FB5_4   STD  RESET
b4d31                           2     11    FB5_5   STD  RESET
b3d6                            3     13    FB5_6   STD  RESET
b3d31                           3     13    FB5_7   STD  RESET
b2d6                            3     13    FB5_9   STD  RESET
b2d31                           3     13    FB5_11  STD  RESET
b1d6                            3     12    FB5_13  STD  RESET
b1d31                           3     12    FB5_16  STD  RESET
pci                             4     6     FB5_18  STD  
b4d5                            2     11    FB6_1   STD  RESET
b4d11                           2     11    FB6_4   STD  RESET
b4d10                           2     11    FB6_6   STD  RESET
b3d5                            3     13    FB6_7   STD  RESET
b3d11                           3     13    FB6_9   STD  RESET
b3d10                           3     13    FB6_11  STD  RESET
b2d5                            3     13    FB6_12  STD  RESET
b2d11                           3     13    FB6_13  STD  RESET
b2d10                           3     13    FB6_15  STD  RESET
b1d5                            3     12    FB6_16  STD  RESET
b1d11                           3     12    FB6_17  STD  RESET
b1d10                           3     12    FB6_18  STD  RESET
ts6i                            2     4     FB7_1   STD  RESET
b4d26                           2     11    FB7_2   STD  RESET
b4d25                           2     11    FB7_3   STD  RESET
b4d24                           2     11    FB7_4   STD  RESET
ta6_xcQ/ta6_xcQ_TRST__$INT      3     6     FB7_6   STD  
b3d7                            3     13    FB7_7   STD  RESET
b3d26                           3     13    FB7_8   STD  RESET

Signal                          Total Total Loc     Pwr  Reg Init
Name                            Pts   Inps          Mode State
b3d25                           3     13    FB7_9   STD  RESET
b3d24                           3     13    FB7_10  STD  RESET
b2d7                            3     13    FB7_11  STD  RESET
b2d26                           3     13    FB7_12  STD  RESET
b2d25                           3     13    FB7_13  STD  RESET
b2d24                           3     13    FB7_14  STD  RESET
b1d26                           3     12    FB7_15  STD  RESET
b1d25                           3     12    FB7_16  STD  RESET
b1d24                           3     12    FB7_17  STD  RESET
$OpTx$FX_DC$217                 4     7     FB7_18  STD  
b4d9                            2     11    FB8_1   STD  RESET
b4d22                           2     11    FB8_4   STD  RESET
b4d21                           2     11    FB8_6   STD  RESET
b3d9                            3     13    FB8_7   STD  RESET
b3d22                           3     13    FB8_9   STD  RESET
b3d21                           3     13    FB8_11  STD  RESET
b2d9                            3     13    FB8_12  STD  RESET
b2d22                           3     13    FB8_13  STD  RESET
b2d21                           3     13    FB8_14  STD  RESET
b1d9                            3     12    FB8_15  STD  RESET
b1d22                           3     12    FB8_16  STD  RESET
b1d21                           3     12    FB8_17  STD  RESET
b1d13                           3     12    FB8_18  STD  RESET
ts6p/ts6p_RSTF__$INT            1     2     FB9_4   STD  
ts6bf                           1     1     FB9_5   STD  RESET
teapm2                          1     1     FB9_6   STD  RESET
teapm                           1     1     FB9_7   STD  RESET
iack6                           1     5     FB9_8   STD  
g3_OBUF/g3_OBUF_SETF__$INT      1     2     FB9_9   STD  
ve7                             2     7     FB9_10  STD  RESET
ve6                             2     7     FB9_11  STD  RESET
ve5                             2     7     FB9_12  STD  RESET
ve4                             2     7     FB9_13  STD  RESET
prst                            2     6     FB9_15  STD  RESET
pcimap                          2     6     FB9_16  STD  RESET
enbi0                           2     7     FB9_18  STD  RESET
vect2                           2     6     FB10_13 STD  RESET
vect1                           2     4     FB10_14 STD  RESET
vect0                           2     6     FB10_15 STD  RESET
vect3                           4     8     FB10_16 STD  RESET

Signal                          Total Total Loc     Pwr  Reg Init
Name                            Pts   Inps          Mode State
ct_irq_xcBUF/ct_irq_xcBUF_TRST  4     8     FB10_18 STD  
b4d14                           2     11    FB11_1  STD  RESET
b3d30                           3     13    FB11_2  STD  RESET
b3d17                           3     13    FB11_3  STD  RESET
b3d16                           3     13    FB11_4  STD  RESET
b3d15                           3     13    FB11_6  STD  RESET
b3d14                           3     13    FB11_7  STD  RESET
b2d30                           3     13    FB11_8  STD  RESET
b2d17                           3     13    FB11_9  STD  RESET
b2d16                           3     13    FB11_13 STD  RESET
b2d15                           3     13    FB11_15 STD  RESET
b2d14                           3     13    FB11_16 STD  RESET
b1d14                           3     12    FB11_18 STD  RESET
taend                           1     5     FB12_7  STD  RESET
tacc0                           1     4     FB12_9  STD  RESET
tacc1                           2     5     FB12_11 STD  RESET
b4d23                           2     11    FB12_13 STD  RESET
tacc2                           3     7     FB12_14 STD  RESET
b3d23                           3     13    FB12_15 STD  RESET
b2d23                           3     13    FB12_16 STD  RESET
b1d23                           3     12    FB12_17 STD  RESET
tacc3                           4     7     FB12_18 STD  RESET
b3d4                            3     13    FB13_1  STD  RESET
b3d3                            3     13    FB13_3  STD  RESET
b3d28                           3     13    FB13_4  STD  RESET
b3d27                           3     13    FB13_5  STD  RESET
b2d4                            3     13    FB13_6  STD  RESET
b2d3                            3     13    FB13_7  STD  RESET
b2d28                           3     13    FB13_9  STD  RESET
b2d27                           3     13    FB13_10 STD  RESET
b1d4                            3     12    FB13_12 STD  RESET
b1d3                            3     12    FB13_13 STD  RESET
b1d28                           3     12    FB13_16 STD  RESET
b1d27                           3     12    FB13_18 STD  RESET
b4d29                           2     11    FB14_1  STD  RESET
b4d19                           2     11    FB14_2  STD  RESET
b4d18                           2     11    FB14_4  STD  RESET
b3d29                           3     13    FB14_5  STD  RESET
b3d20                           3     13    FB14_6  STD  RESET
b3d19                           3     13    FB14_7  STD  RESET

Signal                          Total Total Loc     Pwr  Reg Init
Name                            Pts   Inps          Mode State
b3d18                           3     13    FB14_8  STD  RESET
b2d29                           3     13    FB14_9  STD  RESET
b2d20                           3     13    FB14_10 STD  RESET
b2d19                           3     13    FB14_12 STD  RESET
b2d18                           3     13    FB14_13 STD  RESET
b1d29                           3     12    FB14_16 STD  RESET
b1d19                           3     12    FB14_17 STD  RESET
b1d18                           3     12    FB14_18 STD  RESET
tspm                            1     1     FB15_1  STD  RESET
idhlatch                        1     8     FB15_4  STD  RESET
brst6                           1     2     FB15_5  STD  
brst                            1     5     FB15_6  STD  
itr                             2     9     FB15_7  STD  RESET
icc1                            2     4     FB15_9  STD  RESET
idend                           3     7     FB15_13 STD  RESET
icc2                            3     5     FB15_16 STD  RESET
icc0                            3     6     FB15_17 STD  RESET
icc3                            4     6     FB15_18 STD  RESET
ta6m                            1     1     FB16_2  STD  RESET
b4d8                            2     11    FB16_3  STD  RESET
b4d20                           2     11    FB16_4  STD  RESET
b4d17                           2     11    FB16_7  STD  RESET
b4d16                           2     11    FB16_9  STD  RESET
b4d15                           2     11    FB16_10 STD  RESET
b3d8                            3     13    FB16_12 STD  RESET
b2d8                            3     13    FB16_13 STD  RESET
b1d8                            3     12    FB16_14 STD  RESET
b1d20                           3     12    FB16_15 STD  RESET
b1d17                           3     12    FB16_16 STD  RESET
b1d16                           3     12    FB16_17 STD  RESET
b1d15                           3     12    FB16_18 STD  RESET

** 27 Inputs **

Signal                          Loc     Pin  Pin     Pin     
Name                                    No.  Type    Use     
brslt                           FB1_17  27   I/O     I
ide                             FB2_8   13   I/O     I
bg1                             FB3_2   28   I/O     I
clk                             FB3_10  30   GCK/I/O GCK
pciclk                          FB3_14  32   GCK/I/O GCK
bb                              FB5_2   34   I/O     I
rw                              FB5_5   35   I/O     I
brplx                           FB6_6   138  I/O     I
rst                             FB6_15  143  GSR/I/O GSR/I
tea                             FB7_3   45   I/O     I
a31                             FB7_12  48   I/O     I
a30                             FB7_15  49   I/O     I
a29                             FB9_2   50   I/O     I
a28                             FB9_3   51   I/O     I
a27                             FB9_5   52   I/O     I
a5                              FB9_6   53   I/O     I
a1                              FB9_8   54   I/O     I
a0                              FB9_11  56   I/O     I
inta                            FB14_5  101  I/O     I
intb                            FB14_6  102  I/O     I
intd                            FB14_8  103  I/O     I
intc                            FB14_10 104  I/O     I
r0                              FB15_17 88   I/O     I
r4                              FB16_2  91   I/O     I
r3                              FB16_3  92   I/O     I
r2                              FB16_10 96   I/O     I
r1                              FB16_12 98   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               39/15
Number of signals used by logic mapping into function block:  39
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
ts6c                  1       0   /\2   2     FB1_1         (b)     (b)
tapcc0                1       0     0   4     FB1_2         (b)     (b)
ta6cc0                2       0     0   3     FB1_3         (b)     (b)
stplx                 2       0     0   3     FB1_4         (b)     (b)
tt1                   1       0     0   4     FB1_5   20    I/O     I/O
tt0                   1       0     0   4     FB1_6   21    I/O     I/O
enbi4                 2       0     0   3     FB1_7         (b)     (b)
tm2                   1       0     0   4     FB1_8   22    I/O     I/O
enbi3                 2       0     0   3     FB1_9         (b)     (b)
tm1                   1       0     0   4     FB1_10  23    I/O     I/O
enbi2                 2       0     0   3     FB1_11        (b)     (b)
tm0                   1       0     0   4     FB1_12  24    I/O     I/O
enbi1                 2       0     0   3     FB1_13        (b)     (b)
ieo                   4       0     0   1     FB1_14  25    I/O     O
br60                  2       0     0   3     FB1_15  26    I/O     O
ta6cc1                3       0     0   2     FB1_16        (b)     (b)
bmplx                 4       0   \/1   0     FB1_17  27    I/O     I
ts6p                  8       3<-   0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d20.PIN           14: a31               27: intd 
  2: d17.PIN           15: a5                28: pci 
  3: d22.PIN           16: bmplx             29: plx 
  4: d18.PIN           17: brplx             30: rcs 
  5: d23.PIN           18: brslt             31: rw 
  6: d19.PIN           19: brst6             32: stplx 
  7: tsp.PIN           20: enbi1             33: ta6 
  8: bs1.PIN           21: enbi2             34: ta6cc0 
  9: tap.PIN           22: enbi3             35: ta6cc1 
 10: a27               23: enbi4             36: ts6bf 
 11: a28               24: inta              37: ts6c 
 12: a29               25: intb              38: ts6p 
 13: a30               26: intc              39: ts6p/ts6p_RSTF__$INT 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ts6c                 .........XXXXX.....................X.... 6
tapcc0               ........X.........X........XX........X.. 5
ta6cc0               ..................X........XX...X....XX. 6
stplx                ....X..X......X..............XXX....X... 7
tt1                  ............................X........... 1
tt0                  ............................X........... 1
enbi4                X......X......X.......X......XX.....X... 7
tm2                  ............................X........... 1
enbi3                .....X.X......X......X.......XX.....X... 7
tm1                  ............................X........... 1
enbi2                ...X...X......X.....X........XX.....X... 7
tm0                  ............................X........... 1
enbi1                .X.....X......X....X.........XX.....X... 7
ieo                  ...................XXXXXXXX............. 8
br60                 ................XX.............X........ 3
ta6cc1               ..................X........XX...XX...XX. 7
bmplx                ..X...XX......XX............XXX.....X... 9
ts6p                 .........XXXXX....X.........X...XXXX.XX. 13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               44/10
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d0                  2       0     0   3     FB2_1         (b)     (b)
tap                   4       0     0   1     FB2_2   9     I/O     I/O
tsp                   3       0     0   2     FB2_3   10    I/O     I/O
b3d1                  3       0     0   2     FB2_4         (b)     (b)
burst                 2       0     0   3     FB2_5   11    I/O     O
b3d0                  3       0     0   2     FB2_6   12    I/O     (b)
b2d1                  3       0     0   2     FB2_7         (b)     (b)
b2d0                  3       0     0   2     FB2_8   13    I/O     I
b1d0                  3       0     0   2     FB2_9         (b)     (b)
ct_irq                5       0     0   0     FB2_10  14    I/O     O
vect7                 4       0     0   1     FB2_11        (b)     (b)
bs3                   4       0     0   1     FB2_12  15    I/O     I/O
vect6                 4       0     0   1     FB2_13        (b)     (b)
bs2                   4       0     0   1     FB2_14  16    I/O     O
bs1                   3       0     0   2     FB2_15  17    I/O     I/O
vect5                 4       0     0   1     FB2_16        (b)     (b)
bs0                   2       0     0   3     FB2_17  19    I/O     O
vect4                 4       0     0   1     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d0.PIN            16: b4d0                            31: rw 
  2: d1.PIN            17: b4d1                            32: shift 
  3: ts6.PIN           18: brst                            33: ta6m 
  4: siz0.PIN          19: ct_irq_xcBUF/ct_irq_xcBUF_TRST  34: tacc0 
  5: siz1.PIN          20: enbi1                           35: tacc1 
  6: tsiz0.PIN         21: enbi2                           36: tacc2 
  7: tsiz1.PIN         22: enbi3                           37: tacc3 
  8: ta6.PIN           23: enbi4                           38: tap 
  9: a0                24: inta                            39: tsp 
 10: a1                25: intb                            40: tspm 
 11: b1d0              26: intc                            41: ve4 
 12: b2d0              27: intd                            42: ve5 
 13: b2d1              28: pci                             43: ve6 
 14: b3d0              29: peot                            44: ve7 
 15: b3d1              30: plx                            

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b4d0                 X......X.......X.X..........XXX..XXXX............. 11
tap                  .......X.........X...........X..X....X............ 5
tsp                  ..X..........................X........XX.......... 4
b3d1                 .X.....X......X.XX..........XXXX.XXXX............. 13
burst                ...XX......................X.X.................... 4
b3d0                 X......X.....X.X.X..........XXXX.XXXX............. 13
b2d1                 .X.....X....X.X..X..........XXXX.XXXX............. 13
b2d0                 X......X...X.X...X..........XXXX.XXXX............. 13
b1d0                 X......X..XX.....X...........XXX.XXXX............. 12
ct_irq               ..................XXXXXXXXX....................... 9
vect7                ...................XXXXXXXX................X...... 9
bs3                  .....XX.XX...................X.................... 5
vect6                ...................XXXXXXXX...............X....... 9
bs2                  .....XX.XX...................X.................... 5
bs1                  .....XX.XX...................X.................... 5
vect5                ...................XXXXXXXX..............X........ 9
bs0                  ........XX...................X.................... 3
vect4                ...................XXXXXXXX.............X......... 9
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               38/16
Number of signals used by logic mapping into function block:  38
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
psync                 1       0     0   4     FB3_1         (b)     (b)
peot                  1       0     0   4     FB3_2   28    I/O     I
tscnt                 2       0     0   3     FB3_3         (b)     (b)
shift                 2       0     0   3     FB3_4         (b)     (b)
pcc1                  2       0     0   3     FB3_5         (b)     (b)
pcc0                  2       0     0   3     FB3_6         (b)     (b)
b4d7                  2       0     0   3     FB3_7         (b)     (b)
b4d4                  2       0     0   3     FB3_8         (b)     (b)
b4d30                 2       0     0   3     FB3_9         (b)     (b)
b4d3                  2       0     0   3     FB3_10  30    GCK/I/O GCK
b4d28                 2       0     0   3     FB3_11        (b)     (b)
bgslt                 1       0     0   4     FB3_12  31    I/O     O
b4d27                 2       0     0   3     FB3_13        (b)     (b)
b4d1                  2       0     0   3     FB3_14  32    GCK/I/O GCK
ts6                   2       0     0   3     FB3_15  33    I/O     I/O
pcc2                  3       0     0   2     FB3_16        (b)     (b)
b1d7                  3       0     0   2     FB3_17        (b)     (b)
b1d30                 3       0     0   2     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d1.PIN            14: b4d1              27: pcc2 
  2: d3.PIN            15: b4d27             28: peot 
  3: d30.PIN           16: b4d28             29: plx 
  4: d27.PIN           17: b4d3              30: psync 
  5: d28.PIN           18: b4d30             31: rw 
  6: tsp.PIN           19: b4d4              32: shift 
  7: d4.PIN            20: b4d7              33: tacc0 
  8: ta6.PIN           21: bg1               34: tacc1 
  9: d7.PIN            22: brplx             35: tacc2 
 10: b1d30             23: brslt             36: tacc3 
 11: b1d7              24: brst              37: taend 
 12: b2d30             25: pcc0              38: tscnt 
 13: b2d7              26: pcc1             

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
psync                .......................X....XXX.....X... 5
peot                 .......................XXXX.X........... 5
tscnt                .....X......................X........X.. 3
shift                .......................XXXX.X.X......... 6
pcc1                 .......................XX...XXX......... 5
pcc0                 .......................XXXX.XXX......... 7
b4d7                 .......XX..........X...X...XX.X.XXXX.... 11
b4d4                 ......XX..........X....X...XX.X.XXXX.... 11
b4d30                ..X....X.........X.....X...XX.X.XXXX.... 11
b4d3                 .X.....X........X......X...XX.X.XXXX.... 11
b4d28                ....X..X.......X.......X...XX.X.XXXX.... 11
bgslt                ....................XXX................. 3
b4d27                ...X...X......X........X...XX.X.XXXX.... 11
b4d1                 X......X.....X.........X...XX.X.XXXX.... 11
ts6                  .....X......................X........X.. 3
pcc2                 .......................XXXX.XXX......... 7
b1d7                 .......XX.X.X..........X....X.XXXXXX.... 12
b1d30                ..X....X.X.X...........X....X.XXXXXX.... 12
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               44/10
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d2                  2       0     0   3     FB4_1         (b)     (b)
d0                    4       0     0   1     FB4_2   2     GTS/I/O I/O
b4d13                 2       0     0   3     FB4_3         (b)     (b)
b4d12                 2       0     0   3     FB4_4         (b)     (b)
d1                    4       0     0   1     FB4_5   3     GTS/I/O I/O
d2                    4       0     0   1     FB4_6   4     I/O     I/O
b3d2                  3       0     0   2     FB4_7         (b)     (b)
d3                    4       0     0   1     FB4_8   5     GTS/I/O I/O
b3d13                 3       0     0   2     FB4_9         (b)     (b)
b3d12                 3       0     0   2     FB4_10        (b)     (b)
b2d2                  3       0     0   2     FB4_11        (b)     (b)
d4                    4       0     0   1     FB4_12  6     GTS/I/O I/O
b2d13                 3       0     0   2     FB4_13        (b)     (b)
bi                    1       0     0   4     FB4_14  7     I/O     O
b2d12                 3       0     0   2     FB4_15        (b)     (b)
b1d2                  3       0     0   2     FB4_16        (b)     (b)
b1d12                 3       0     0   2     FB4_17        (b)     (b)
b1d1                  3       0     0   2     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$217   16: b1d3              31: peot 
  2: d1.PIN            17: b1d4              32: plx 
  3: d12.PIN           18: b2d1              33: rw 
  4: d13.PIN           19: b2d12             34: shift 
  5: d2.PIN            20: b2d13             35: tacc0 
  6: id0.PIN           21: b2d2              36: tacc1 
  7: id1.PIN           22: b3d12             37: tacc2 
  8: id2.PIN           23: b3d13             38: tacc3 
  9: id3.PIN           24: b3d2              39: ts6i 
 10: id4.PIN           25: b4d12             40: vect0 
 11: ta6.PIN           26: b4d13             41: vect1 
 12: b1d0              27: b4d2              42: vect2 
 13: b1d1              28: brst              43: vect3 
 14: b1d12             29: iack6             44: vect4 
 15: b1d2              30: ieo              

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b4d2                 ....X.....X...............XX..XXX.XXXX............ 11
d0                   X....X.....X...............XXX.XX.....XX.......... 10
b4d13                ...X......X..............X.X..XXX.XXXX............ 11
b4d12                ..X.......X.............X..X..XXX.XXXX............ 11
d1                   X.....X.....X..............XXX.XX.....X.X......... 10
d2                   X......X......X............XXX.XX.....X..X........ 10
b3d2                 ....X.....X............X..XX..XXXXXXXX............ 13
d3                   X.......X......X...........XXX.XX.....X...X....... 10
b3d13                ...X......X...........X..X.X..XXXXXXXX............ 13
b3d12                ..X.......X..........X..X..X..XXXXXXXX............ 13
b2d2                 ....X.....X.........X..X...X..XXXXXXXX............ 13
d4                   X........X......X..........XXX.XX.....X....X...... 10
b2d13                ...X......X........X..X....X..XXXXXXXX............ 13
bi                   ...............................X.................. 1
b2d12                ..X.......X.......X..X.....X..XXXXXXXX............ 13
b1d2                 ....X.....X...X.....X......X...XXXXXXX............ 12
b1d12                ..X.......X..X....X........X...XXXXXXX............ 12
b1d1                 .X........X.X....X.........X...XXXXXXX............ 12
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               41/13
Number of signals used by logic mapping into function block:  41
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
rcs                   1       0     0   4     FB5_1         (b)     (b)
tapcc1                2       0     0   3     FB5_2   34    I/O     I
plx                   2       0     0   3     FB5_3         (b)     (b)
b4d6                  2       0     0   3     FB5_4         (b)     (b)
b4d31                 2       0     0   3     FB5_5   35    I/O     I
b3d6                  3       0     0   2     FB5_6         (b)     (b)
b3d31                 3       0     0   2     FB5_7         (b)     (b)
pclk                  0       0     0   5     FB5_8   38    GCK/I/O GCK/O
b2d6                  3       0     0   2     FB5_9         (b)     (b)
tsiz1                 2       0     0   3     FB5_10  39    I/O     I/O
b2d31                 3       0     0   2     FB5_11        (b)     (b)
tsiz0                 2       0     0   3     FB5_12  40    I/O     I/O
b1d6                  3       0     0   2     FB5_13        (b)     (b)
siz1                  2       0     0   3     FB5_14  41    I/O     I/O
bdip                  5       0     0   0     FB5_15  43    I/O     O
b1d31                 3       0     0   2     FB5_16        (b)     (b)
siz0                  2       0     0   3     FB5_17  44    I/O     I/O
pci                   4       0     0   1     FB5_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d31.PIN           15: b1d6              29: pcimap 
  2: siz0.PIN          16: b2d31             30: peot 
  3: siz1.PIN          17: b2d6              31: plx 
  4: tsiz0.PIN         18: b3d31             32: rw 
  5: tsiz1.PIN         19: b3d6              33: shift 
  6: ta6.PIN           20: b4d31             34: tacc0 
  7: d6.PIN            21: b4d6              35: tacc1 
  8: tap.PIN           22: bb                36: tacc2 
  9: a27               23: bdip              37: tacc3 
 10: a28               24: bg1               38: tapcc0 
 11: a29               25: brplx             39: tapcc1 
 12: a30               26: brst              40: ts6p 
 13: a31               27: brst6             41: tsp 
 14: b1d31             28: pci              

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
rcs                  ........XXXXX..................................... 5
tapcc1               .......X..................XX..X......X.X.......... 6
plx                  .....................X.XX.....X................... 4
b4d6                 .....XX.............X....X...XXX.XXXX............. 11
b4d31                X....X.............X.....X...XXX.XXXX............. 11
b3d6                 .....XX...........X.X....X...XXXXXXXX............. 13
b3d31                X....X...........X.X.....X...XXXXXXXX............. 13
pclk                 .................................................. 0
b2d6                 .....XX.........X.X......X...XXXXXXXX............. 13
tsiz1                .X........................XX..X................... 4
b2d31                X....X.........X.X.......X...XXXXXXXX............. 13
tsiz0                ..X.......................XX..X................... 4
b1d6                 .....XX.......X.X........X....XXXXXXX............. 12
siz1                 ...X.....................X....X................... 3
bdip                 .......X..............X...XX..X......XX.X......... 8
b1d31                X....X.......X.X.........X....XXXXXXX............. 12
siz0                 ....X....................X....X................... 3
pci                  ........XXXXX...............X..................... 6
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               44/10
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d5                  2       0     0   3     FB6_1         (b)     (b)
teap                  2       0     0   3     FB6_2   135   I/O     O
bgplx                 1       0     0   4     FB6_3   136   I/O     O
b4d11                 2       0     0   3     FB6_4         (b)     (b)
d8                    3       0     0   2     FB6_5   137   I/O     I/O
b4d10                 2       0     0   3     FB6_6   138   I/O     I
b3d5                  3       0     0   2     FB6_7         (b)     (b)
d7                    4       0     0   1     FB6_8   139   I/O     I/O
b3d11                 3       0     0   2     FB6_9         (b)     (b)
d6                    4       0     0   1     FB6_10  140   I/O     I/O
b3d10                 3       0     0   2     FB6_11        (b)     (b)
b2d5                  3       0     0   2     FB6_12        (b)     (b)
b2d11                 3       0     0   2     FB6_13        (b)     (b)
d5                    4       0     0   1     FB6_14  142   I/O     I/O
b2d10                 3       0     0   2     FB6_15  143   GSR/I/O GSR/I
b1d5                  3       0     0   2     FB6_16        (b)     (b)
b1d11                 3       0     0   2     FB6_17        (b)     (b)
b1d10                 3       0     0   2     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$217   16: b2d10             31: plx 
  2: d10.PIN           17: b2d11             32: rw 
  3: d11.PIN           18: b2d5              33: shift 
  4: id5.PIN           19: b3d10             34: tacc0 
  5: id6.PIN           20: b3d11             35: tacc1 
  6: id7.PIN           21: b3d5              36: tacc2 
  7: id8.PIN           22: b4d10             37: tacc3 
  8: d5.PIN            23: b4d11             38: tea 
  9: ta6.PIN           24: b4d5              39: teap 
 10: b1d10             25: bg1               40: teapm2 
 11: b1d11             26: brplx             41: ts6i 
 12: b1d5              27: brst              42: vect5 
 13: b1d6              28: iack6             43: vect6 
 14: b1d7              29: ieo               44: vect7 
 15: b1d8              30: peot             

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b4d5                 .......XX..............X..X..XXX.XXXX............. 11
teap                 .....................................XXX.......... 3
bgplx                ........................XX........................ 2
b4d11                ..X.....X.............X...X..XXX.XXXX............. 11
d8                   X.....X.......X...........X...XX........X......... 7
b4d10                .X......X............X....X..XXX.XXXX............. 11
b3d5                 .......XX...........X..X..X..XXXXXXXX............. 13
d7                   X....X.......X............XXX.XX........X..X...... 10
b3d11                ..X.....X..........X..X...X..XXXXXXXX............. 13
d6                   X...X.......X.............XXX.XX........X.X....... 10
b3d10                .X......X.........X..X....X..XXXXXXXX............. 13
b2d5                 .......XX........X..X.....X..XXXXXXXX............. 13
b2d11                ..X.....X.......X..X......X..XXXXXXXX............. 13
d5                   X..X.......X..............XXX.XX........XX........ 10
b2d10                .X......X......X..X.......X..XXXXXXXX............. 13
b1d5                 .......XX..X.....X........X...XXXXXXX............. 12
b1d11                ..X.....X.X.....X.........X...XXXXXXX............. 12
b1d10                .X......XX.....X..........X...XXXXXXX............. 12
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               43/11
Number of signals used by logic mapping into function block:  43
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
ts6i                  2       0     0   3     FB7_1         (b)     (b)
b4d26                 2       0     0   3     FB7_2         (b)     (b)
b4d25                 2       0     0   3     FB7_3   45    I/O     I
b4d24                 2       0     0   3     FB7_4         (b)     (b)
ta6                   5       0     0   0     FB7_5   46    I/O     I/O
ta6_xcQ/ta6_xcQ_TRST__$INT
                      3       0     0   2     FB7_6         (b)     (b)
b3d7                  3       0     0   2     FB7_7         (b)     (b)
b3d26                 3       0     0   2     FB7_8         (b)     (b)
b3d25                 3       0     0   2     FB7_9         (b)     (b)
b3d24                 3       0     0   2     FB7_10        (b)     (b)
b2d7                  3       0     0   2     FB7_11        (b)     (b)
b2d26                 3       0     0   2     FB7_12  48    I/O     I
b2d25                 3       0     0   2     FB7_13        (b)     (b)
b2d24                 3       0     0   2     FB7_14        (b)     (b)
b1d26                 3       0     0   2     FB7_15  49    I/O     I
b1d25                 3       0     0   2     FB7_16        (b)     (b)
b1d24                 3       0     0   2     FB7_17        (b)     (b)
$OpTx$FX_DC$217       4       0     0   1     FB7_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d24.PIN           16: b3d26             30: rcs 
  2: d25.PIN           17: b3d7              31: rw 
  3: d26.PIN           18: b4d24             32: shift 
  4: ta6.PIN           19: b4d25             33: ta6 
  5: tap.PIN           20: b4d26             34: ta6_xcQ/ta6_xcQ_TRST__$INT 
  6: d7.PIN            21: b4d7              35: tacc0 
  7: b1d24             22: brst              36: tacc1 
  8: b1d25             23: iack6             37: tacc2 
  9: b1d26             24: ide               38: tacc3 
 10: b2d24             25: idend             39: tap 
 11: b2d25             26: ieo               40: ts6bf 
 12: b2d26             27: pci               41: ts6c 
 13: b2d7              28: peot              42: ts6i 
 14: b3d24             29: plx               43: ts6p 
 15: b3d25            

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
ts6i                 .......................X........X......X.X........ 4
b4d26                ..XX...............X.X.....XX.X...XXXX............ 11
b4d25                .X.X..............X..X.....XX.X...XXXX............ 11
b4d24                X..X.............X...X.....XX.X...XXXX............ 11
ta6                  ....X.................X.XX...X..XX.....XXXX....... 11
ta6_xcQ/ta6_xcQ_TRST__$INT 
                     ......................X..XX.XX...........X........ 6
b3d7                 ...X.X..........X...XX.....XX.XX..XXXX............ 13
b3d26                ..XX...........X...X.X.....XX.XX..XXXX............ 13
b3d25                .X.X..........X...X..X.....XX.XX..XXXX............ 13
b3d24                X..X.........X...X...X.....XX.XX..XXXX............ 13
b2d7                 ...X.X......X...X....X.....XX.XX..XXXX............ 13
b2d26                ..XX.......X...X.....X.....XX.XX..XXXX............ 13
b2d25                .X.X......X...X......X.....XX.XX..XXXX............ 13
b2d24                X..X.....X...X.......X.....XX.XX..XXXX............ 13
b1d26                ..XX....X..X.........X......X.XX..XXXX............ 12
b1d25                .X.X...X..X..........X......X.XX..XXXX............ 12
b1d24                X..X..X..X...........X......X.XX..XXXX............ 12
$OpTx$FX_DC$217      .....................XX..X..XX........X..X........ 7
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               38/16
Number of signals used by logic mapping into function block:  38
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d9                  2       0     0   3     FB8_1         (b)     (b)
d13                   3       0     0   2     FB8_2   130   I/O     I/O
d12                   3       0     0   2     FB8_3   131   I/O     I/O
b4d22                 2       0     0   3     FB8_4         (b)     (b)
d11                   3       0     0   2     FB8_5   132   I/O     I/O
b4d21                 2       0     0   3     FB8_6         (b)     (b)
b3d9                  3       0     0   2     FB8_7         (b)     (b)
d10                   3       0     0   2     FB8_8   133   I/O     I/O
b3d22                 3       0     0   2     FB8_9         (b)     (b)
d9                    3       0     0   2     FB8_10  134   I/O     I/O
b3d21                 3       0     0   2     FB8_11        (b)     (b)
b2d9                  3       0     0   2     FB8_12        (b)     (b)
b2d22                 3       0     0   2     FB8_13        (b)     (b)
b2d21                 3       0     0   2     FB8_14        (b)     (b)
b1d9                  3       0     0   2     FB8_15        (b)     (b)
b1d22                 3       0     0   2     FB8_16        (b)     (b)
b1d21                 3       0     0   2     FB8_17        (b)     (b)
b1d13                 3       0     0   2     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$217   14: b1d12             27: b4d22 
  2: d13.PIN           15: b1d13             28: b4d9 
  3: d21.PIN           16: b1d21             29: brst 
  4: d22.PIN           17: b1d22             30: peot 
  5: id9.PIN           18: b1d9              31: plx 
  6: id10.PIN          19: b2d13             32: rw 
  7: id11.PIN          20: b2d21             33: shift 
  8: id12.PIN          21: b2d22             34: tacc0 
  9: id13.PIN          22: b2d9              35: tacc1 
 10: ta6.PIN           23: b3d21             36: tacc2 
 11: d9.PIN            24: b3d22             37: tacc3 
 12: b1d10             25: b3d9              38: ts6i 
 13: b1d11             26: b4d21            

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
b4d9                 .........XX................XXXXX.XXXX... 11
d13                  X.......X.....X.............X.XX.....X.. 7
d12                  X......X.....X..............X.XX.....X.. 7
b4d22                ...X.....X................X.XXXX.XXXX... 11
d11                  X.....X.....X...............X.XX.....X.. 7
b4d21                ..X......X...............X..XXXX.XXXX... 11
b3d9                 .........XX.............X..XXXXXXXXXX... 13
d10                  X....X.....X................X.XX.....X.. 7
b3d22                ...X.....X.............X..X.XXXXXXXXX... 13
d9                   X...X............X..........X.XX.....X.. 7
b3d21                ..X......X............X..X..XXXXXXXXX... 13
b2d9                 .........XX..........X..X...XXXXXXXXX... 13
b2d22                ...X.....X..........X..X....XXXXXXXXX... 13
b2d21                ..X......X.........X..X.....XXXXXXXXX... 13
b1d9                 .........XX......X...X......X.XXXXXXX... 12
b1d22                ...X.....X......X...X.......X.XXXXXXX... 12
b1d21                ..X......X.....X...X........X.XXXXXXX... 12
b1d13                .X.......X....X...X.........X.XXXXXXX... 12
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB9  ***********************************
Number of function block inputs used/remaining:               31/23
Number of signals used by logic mapping into function block:  31
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB9_1         (b)     
(unused)              0       0     0   5     FB9_2   50    I/O     I
(unused)              0       0     0   5     FB9_3   51    I/O     I
ts6p/ts6p_RSTF__$INT
                      1       0     0   4     FB9_4         (b)     (b)
ts6bf                 1       0     0   4     FB9_5   52    I/O     I
teapm2                1       0     0   4     FB9_6   53    I/O     I
teapm                 1       0     0   4     FB9_7         (b)     (b)
iack6                 1       0     0   4     FB9_8   54    I/O     I
g3_OBUF/g3_OBUF_SETF__$INT
                      1       0     0   4     FB9_9         (b)     (b)
ve7                   2       0     0   3     FB9_10        (b)     (b)
ve6                   2       0     0   3     FB9_11  56    I/O     I
ve5                   2       0     0   3     FB9_12  57    I/O     (b)
ve4                   2       0     0   3     FB9_13        (b)     (b)
cs1                   1       0     0   4     FB9_14  58    I/O     O
prst                  2       0     0   3     FB9_15        (b)     (b)
pcimap                2       0     0   3     FB9_16        (b)     (b)
cs0                   1       0     0   4     FB9_17  59    I/O     O
enbi0                 2       0     0   3     FB9_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d0.PIN            12: d6.PIN            22: rst 
  2: tm0.PIN           13: bs1.PIN           23: rw 
  3: tm1.PIN           14: bs3.PIN           24: tea 
  4: tm2.PIN           15: d7.PIN            25: teap 
  5: tt0.PIN           16: a5                26: teapm 
  6: tt1.PIN           17: enbi0             27: ts6c 
  7: ts6.PIN           18: ide               28: ve4 
  8: d2.PIN            19: pcimap            29: ve5 
  9: d16.PIN           20: prst              30: ve6 
 10: d4.PIN            21: rcs               31: ve7 
 11: d5.PIN           

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
ts6p/ts6p_RSTF__$INT 
                     .....................X.X................ 2
ts6bf                ......X................................. 1
teapm2               .........................X.............. 1
teapm                ........................X............... 1
iack6                .XXXXX.................................. 5
g3_OBUF/g3_OBUF_SETF__$INT 
                     ...................X.X.................. 2
ve7                  .............XXX....X.X...X...X......... 7
ve6                  ...........X.X.X....X.X...X..X.......... 7
ve5                  ..........X..X.X....X.X...X.X........... 7
ve4                  .........X...X.X....X.X...XX............ 7
cs1                  ...............X.X...................... 2
prst                 X..............X...XX.X...X............. 6
pcimap               .......X.......X..X.X.X...X............. 6
cs0                  ...............X.X...................... 2
enbi0                ........X...X..XX...X.X...X............. 7
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB10 ***********************************
Number of function block inputs used/remaining:               44/10
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB10_1        (b)     
d22                   5       0     0   0     FB10_2  117   I/O     I/O
d21                   4       0     0   1     FB10_3  118   I/O     I/O
(unused)              0       0     0   5     FB10_4        (b)     
d20                   5       0     0   0     FB10_5  119   I/O     I/O
d19                   5       0     0   0     FB10_6  120   I/O     I/O
(unused)              0       0     0   5     FB10_7        (b)     
d18                   5       0     0   0     FB10_8  121   I/O     I/O
(unused)              0       0     0   5     FB10_9        (b)     
d17                   5       0     0   0     FB10_10 124   I/O     I/O
d16                   5       0     0   0     FB10_11 125   I/O     I/O
d15                   3       0     0   2     FB10_12 126   I/O     I/O
vect2                 2       0     0   3     FB10_13       (b)     (b)
vect1                 2       0     0   3     FB10_14 128   I/O     (b)
vect0                 2       0     0   3     FB10_15       (b)     (b)
vect3                 4       0     0   1     FB10_16       (b)     (b)
d14                   3       0     0   2     FB10_17 129   I/O     I/O
ct_irq_xcBUF/ct_irq_xcBUF_TRST
                      4       0     0   1     FB10_18       (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$217   16: b1d18             31: enbi1 
  2: id0.PIN           17: b1d19             32: enbi2 
  3: id1.PIN           18: b1d20             33: enbi3 
  4: id2.PIN           19: b1d21             34: enbi4 
  5: id3.PIN           20: b1d22             35: idhlatch 
  6: id4.PIN           21: bmplx             36: inta 
  7: id5.PIN           22: brst              37: intb 
  8: id6.PIN           23: d16               38: intc 
  9: id14.PIN          24: d17               39: intd 
 10: id15.PIN          25: d18               40: plx 
 11: a5                26: d19               41: rw 
 12: b1d14             27: d20               42: ta6 
 13: b1d15             28: d21               43: ts6c 
 14: b1d16             29: d22               44: ts6i 
 15: b1d17             30: enbi0            

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
d22                  X......X..X........XXX......X.....X....XXXXX...... 13
d21                  X.....X...........X..X.....X......X....XXX.X...... 10
d20                  X....X....X......X...X....X......XX....XXXXX...... 13
d19                  X...X.....X.....X....X...X......X.X....XXXXX...... 13
d18                  X..X......X....X.....X..X......X..X....XXXXX...... 13
d17                  X.X.......X...X......X.X......X...X....XXXXX...... 13
d16                  XX........X..X.......XX......X....X....XXXXX...... 13
d15                  X........X..X........X.................XX..X...... 7
vect2                ................................XX.XXXX........... 6
vect1                ..............................XX...XX............. 4
vect0                ...............................X.X.XXXX........... 6
vect3                ..............................XXXX.XXXX........... 8
d14                  X.......X..X.........X.................XX..X...... 7
ct_irq_xcBUF/ct_irq_xcBUF_TRST 
                     ..............................XXXX.XXXX........... 8
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB11 ***********************************
Number of function block inputs used/remaining:               44/10
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d14                 2       0     0   3     FB11_1        (b)     (b)
b3d30                 3       0     0   2     FB11_2        (b)     (b)
b3d17                 3       0     0   2     FB11_3  60    I/O     (b)
b3d16                 3       0     0   2     FB11_4        (b)     (b)
ior                   2       0     0   3     FB11_5  61    I/O     O
b3d15                 3       0     0   2     FB11_6        (b)     (b)
b3d14                 3       0     0   2     FB11_7        (b)     (b)
b2d30                 3       0     0   2     FB11_8        (b)     (b)
b2d17                 3       0     0   2     FB11_9        (b)     (b)
iow                   2       0     0   3     FB11_10 64    I/O     O
id15                  4       0     0   1     FB11_11 66    I/O     I/O
id0                   4       0     0   1     FB11_12 68    I/O     I/O
b2d16                 3       0     0   2     FB11_13       (b)     (b)
id14                  4       0     0   1     FB11_14 69    I/O     I/O
b2d15                 3       0     0   2     FB11_15       (b)     (b)
b2d14                 3       0     0   2     FB11_16       (b)     (b)
id1                   4       0     0   1     FB11_17 70    I/O     I/O
b1d14                 3       0     0   2     FB11_18       (b)     (b)

Signals Used by Logic in Function Block
  1: d0.PIN            16: b2d30             31: icc3 
  2: d1.PIN            17: b3d14             32: ide 
  3: d14.PIN           18: b3d15             33: ior 
  4: d15.PIN           19: b3d16             34: iow 
  5: d16.PIN           20: b3d17             35: itr 
  6: d17.PIN           21: b3d30             36: peot 
  7: d30.PIN           22: b4d14             37: plx 
  8: d31.PIN           23: b4d15             38: rw 
  9: ta6.PIN           24: b4d16             39: shift 
 10: a1                25: b4d17             40: tacc0 
 11: b1d14             26: b4d30             41: tacc1 
 12: b2d14             27: brst              42: tacc2 
 13: b2d15             28: icc0              43: tacc3 
 14: b2d16             29: icc1              44: ts6i 
 15: b2d17             30: icc2             

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b4d14                ..X.....X............X....X........XXX.XXXX....... 11
b3d30                ......X.X...........X....XX........XXXXXXXX....... 13
b3d17                .....X..X..........X....X.X........XXXXXXXX....... 13
b3d16                ....X...X.........X....X..X........XXXXXXXX....... 13
ior                  ...........................XXXX.X....X.....X...... 7
b3d15                ...X....X........X....X...X........XXXXXXXX....... 13
b3d14                ..X.....X.......X....X....X........XXXXXXXX....... 13
b2d30                ......X.X......X....X.....X........XXXXXXXX....... 13
b2d17                .....X..X.....X....X......X........XXXXXXXX....... 13
iow                  ...........................XXXX..X...X.....X...... 7
id15                 ...X...X.X.....................X..X..X.....X...... 7
id0                  X...X....X.....................X..X..X.....X...... 7
b2d16                ....X...X....X....X.......X........XXXXXXXX....... 13
id14                 ..X...X..X.....................X..X..X.....X...... 7
b2d15                ...X....X...X....X........X........XXXXXXXX....... 13
b2d14                ..X.....X..X....X.........X........XXXXXXXX....... 13
id1                  .X...X...X.....................X..X..X.....X...... 7
b1d14                ..X.....X.XX..............X.........XXXXXXX....... 12
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB12 ***********************************
Number of function block inputs used/remaining:               44/10
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB12_1        (b)     
d28                   5       0     0   0     FB12_2  110   I/O     I/O
d27                   5       0     0   0     FB12_3  111   I/O     I/O
(unused)              0       0     0   5     FB12_4        (b)     
d26                   5       0     0   0     FB12_5  112   I/O     I/O
(unused)              0       0     0   5     FB12_6        (b)     
taend                 1       0     0   4     FB12_7        (b)     (b)
d25                   5       0     0   0     FB12_8  113   I/O     I/O
tacc0                 1       0     0   4     FB12_9        (b)     (b)
d24                   4       0     0   1     FB12_10 115   I/O     I/O
tacc1                 2       0     0   3     FB12_11       (b)     (b)
d23                   5       0     0   0     FB12_12 116   I/O     I/O
b4d23                 2       0     0   3     FB12_13       (b)     (b)
tacc2                 3       0     0   2     FB12_14       (b)     (b)
b3d23                 3       0     0   2     FB12_15       (b)     (b)
b2d23                 3       0     0   2     FB12_16       (b)     (b)
b1d23                 3       0     0   2     FB12_17       (b)     (b)
tacc3                 4       0     0   1     FB12_18       (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$217   16: b1d28             31: intd 
  2: d23.PIN           17: b2d23             32: peot 
  3: id7.PIN           18: b3d23             33: plx 
  4: id8.PIN           19: b4d23             34: rw 
  5: id9.PIN           20: brst              35: shift 
  6: id10.PIN          21: d23               36: stplx 
  7: id11.PIN          22: d24               37: ta6 
  8: id12.PIN          23: d25               38: tacc0 
  9: ta6.PIN           24: d26               39: tacc1 
 10: a5                25: d27               40: tacc2 
 11: b1d23             26: d28               41: tacc3 
 12: b1d24             27: idhlatch          42: taend 
 13: b1d25             28: inta              43: ts6c 
 14: b1d26             29: intb              44: ts6i 
 15: b1d27             30: intc             

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
d28                  X......X.X.....X...X.....XX...X.XX..X.....XX...... 13
d27                  X.....X..X....X....X....X.X..X..XX..X.....XX...... 13
d26                  X....X...X...X.....X...X..X.X...XX..X.....XX...... 13
taend                .....................................XXXXX........ 5
d25                  X...X....X..X......X..X...XX....XX..X.....XX...... 13
tacc0                ........X..........X............X....X............ 4
d24                  X..X.......X.......X.X....X.....XX..X......X...... 10
tacc1                ........X..........X............X....XX........... 5
d23                  X.X......XX........XX.....X.....XX.XX.....XX...... 13
b4d23                .X......X.........XX...........XXX...XXXX......... 11
tacc2                ........X..........X............X....XXXX......... 7
b3d23                .X......X........XXX...........XXXX..XXXX......... 13
b2d23                .X......X.......XX.X...........XXXX..XXXX......... 13
b1d23                .X......X.X.....X..X............XXX..XXXX......... 12
tacc3                ........X..........X............X....XXXX......... 7
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB13 ***********************************
Number of function block inputs used/remaining:               42/12
Number of signals used by logic mapping into function block:  42
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b3d4                  3       0     0   2     FB13_1        (b)     (b)
id13                  4       0     0   1     FB13_2  71    I/O     I/O
b3d3                  3       0     0   2     FB13_3        (b)     (b)
b3d28                 3       0     0   2     FB13_4        (b)     (b)
b3d27                 3       0     0   2     FB13_5        (b)     (b)
b2d4                  3       0     0   2     FB13_6        (b)     (b)
b2d3                  3       0     0   2     FB13_7        (b)     (b)
id2                   4       0     0   1     FB13_8  74    I/O     I/O
b2d28                 3       0     0   2     FB13_9        (b)     (b)
b2d27                 3       0     0   2     FB13_10       (b)     (b)
id12                  4       0     0   1     FB13_11 75    I/O     I/O
b1d4                  3       0     0   2     FB13_12       (b)     (b)
b1d3                  3       0     0   2     FB13_13       (b)     (b)
id3                   4       0     0   1     FB13_14 76    I/O     I/O
id11                  4       0     0   1     FB13_15 77    I/O     I/O
b1d28                 3       0     0   2     FB13_16       (b)     (b)
id4                   4       0     0   1     FB13_17 78    I/O     I/O
b1d27                 3       0     0   2     FB13_18       (b)     (b)

Signals Used by Logic in Function Block
  1: d11.PIN           15: b1d27             29: b4d3 
  2: d12.PIN           16: b1d28             30: b4d4 
  3: d13.PIN           17: b1d3              31: brst 
  4: d2.PIN            18: b1d4              32: ide 
  5: d20.PIN           19: b2d27             33: itr 
  6: d18.PIN           20: b2d28             34: peot 
  7: d19.PIN           21: b2d3              35: plx 
  8: d3.PIN            22: b2d4              36: rw 
  9: d27.PIN           23: b3d27             37: shift 
 10: d28.PIN           24: b3d28             38: tacc0 
 11: d29.PIN           25: b3d3              39: tacc1 
 12: d4.PIN            26: b3d4              40: tacc2 
 13: ta6.PIN           27: b4d27             41: tacc3 
 14: a1                28: b4d28             42: ts6i 

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b3d4                 ...........XX............X...XX..XXXXXXXX......... 13
id13                 ..X.......X..X.................XX..X.....X........ 7
b3d3                 .......X....X...........X...X.X..XXXXXXXX......... 13
b3d28                .........X..X..........X...X..X..XXXXXXXX......... 13
b3d27                ........X...X.........X...X...X..XXXXXXXX......... 13
b2d4                 ...........XX........X...X....X..XXXXXXXX......... 13
b2d3                 .......X....X.......X...X.....X..XXXXXXXX......... 13
id2                  ...X.X.......X.................XX..X.....X........ 7
b2d28                .........X..X......X...X......X..XXXXXXXX......... 13
b2d27                ........X...X.....X...X.......X..XXXXXXXX......... 13
id12                 .X.......X...X.................XX..X.....X........ 7
b1d4                 ...........XX....X...X........X...XXXXXXX......... 12
b1d3                 .......X....X...X...X.........X...XXXXXXX......... 12
id3                  ......XX.....X.................XX..X.....X........ 7
id11                 X.......X....X.................XX..X.....X........ 7
b1d28                .........X..X..X...X..........X...XXXXXXX......... 12
id4                  ....X......X.X.................XX..X.....X........ 7
b1d27                ........X...X.X...X...........X...XXXXXXX......... 12
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB14 ***********************************
Number of function block inputs used/remaining:               43/11
Number of signals used by logic mapping into function block:  43
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d29                 2       0     0   3     FB14_1        (b)     (b)
b4d19                 2       0     0   3     FB14_2        (b)     (b)
pcirst                1       0     0   4     FB14_3  100   I/O     O
b4d18                 2       0     0   3     FB14_4        (b)     (b)
b3d29                 3       0     0   2     FB14_5  101   I/O     I
b3d20                 3       0     0   2     FB14_6  102   I/O     I
b3d19                 3       0     0   2     FB14_7        (b)     (b)
b3d18                 3       0     0   2     FB14_8  103   I/O     I
b2d29                 3       0     0   2     FB14_9        (b)     (b)
b2d20                 3       0     0   2     FB14_10 104   I/O     I
d31                   4       0     0   1     FB14_11 105   I/O     I/O
b2d19                 3       0     0   2     FB14_12       (b)     (b)
b2d18                 3       0     0   2     FB14_13       (b)     (b)
d30                   4       0     0   1     FB14_14 106   I/O     I/O
d29                   4       0     0   1     FB14_15 107   I/O     I/O
b1d29                 3       0     0   2     FB14_16       (b)     (b)
b1d19                 3       0     0   2     FB14_17       (b)     (b)
b1d18                 3       0     0   2     FB14_18       (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$217   16: b2d19             30: d31 
  2: d20.PIN           17: b2d20             31: idhlatch 
  3: d18.PIN           18: b2d29             32: peot 
  4: d19.PIN           19: b3d18             33: plx 
  5: d29.PIN           20: b3d19             34: prst 
  6: id13.PIN          21: b3d20             35: rst 
  7: id14.PIN          22: b3d29             36: rw 
  8: id15.PIN          23: b4d18             37: shift 
  9: ta6.PIN           24: b4d19             38: ta6 
 10: b1d18             25: b4d20             39: tacc0 
 11: b1d19             26: b4d29             40: tacc1 
 12: b1d29             27: brst              41: tacc2 
 13: b1d30             28: d29               42: tacc3 
 14: b1d31             29: d30               43: ts6i 
 15: b2d18            

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b4d29                ....X...X................XX....XX..X..XXXX........ 11
b4d19                ...X....X..............X..X....XX..X..XXXX........ 11
pcirst               .................................XX............... 2
b4d18                ..X.....X.............X...X....XX..X..XXXX........ 11
b3d29                ....X...X............X...XX....XX..XX.XXXX........ 13
b3d20                .X......X...........X...X.X....XX..XX.XXXX........ 13
b3d19                ...X....X..........X...X..X....XX..XX.XXXX........ 13
b3d18                ..X.....X.........X...X...X....XX..XX.XXXX........ 13
b2d29                ....X...X........X...X....X....XX..XX.XXXX........ 13
b2d20                .X......X.......X...X.....X....XX..XX.XXXX........ 13
d31                  X......X.....X............X..XX.X..X.X....X....... 10
b2d19                ...X....X......X...X......X....XX..XX.XXXX........ 13
b2d18                ..X.....X.....X...X.......X....XX..XX.XXXX........ 13
d30                  X.....X.....X.............X.X.X.X..X.X....X....... 10
d29                  X....X.....X..............XX..X.X..X.X....X....... 10
b1d29                ....X...X..X.....X........X.....X..XX.XXXX........ 12
b1d19                ...X....X.X....X..........X.....X..XX.XXXX........ 12
b1d18                ..X.....XX....X...........X.....X..XX.XXXX........ 12
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB15 ***********************************
Number of function block inputs used/remaining:               43/11
Number of signals used by logic mapping into function block:  43
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
tspm                  1       0     0   4     FB15_1        (b)     (b)
id10                  4       0     0   1     FB15_2  79    I/O     I/O
id5                   4       0     0   1     FB15_3  80    I/O     I/O
idhlatch              1       0     0   4     FB15_4        (b)     (b)
brst6                 1       0     0   4     FB15_5        (b)     (b)
brst                  1       0     0   4     FB15_6        (b)     (b)
itr                   2       0     0   3     FB15_7        (b)     (b)
id9                   4       0     0   1     FB15_8  81    I/O     I/O
icc1                  2       0     0   3     FB15_9        (b)     (b)
id6                   4       0     0   1     FB15_10 82    I/O     I/O
id8                   4       0     0   1     FB15_11 83    I/O     I/O
id7                   4       0     0   1     FB15_12 85    I/O     I/O
idend                 3       0     0   2     FB15_13       (b)     (b)
ccs                   1       0   \/1   3     FB15_14 86    I/O     O
g0                    7       2<-   0   0     FB15_15 87    I/O     O
icc2                  3       0   /\1   1     FB15_16       (b)     (b)
icc0                  3       0     0   2     FB15_17 88    I/O     I
icc3                  4       0     0   1     FB15_18       (b)     (b)

Signals Used by Logic in Function Block
  1: d10.PIN           16: a27                         30: icc3 
  2: d21.PIN           17: a28                         31: ide 
  3: d22.PIN           18: a29                         32: itr 
  4: d23.PIN           19: a30                         33: pci 
  5: d24.PIN           20: a31                         34: plx 
  6: d25.PIN           21: g0                          35: r0 
  7: d26.PIN           22: g1                          36: r1 
  8: d5.PIN            23: g2                          37: r2 
  9: siz0.PIN          24: g3                          38: r3 
 10: siz1.PIN          25: g3_OBUF/g3_OBUF_SETF__$INT  39: r4 
 11: d6.PIN            26: g4                          40: rw 
 12: d7.PIN            27: icc0                        41: ta6 
 13: d8.PIN            28: icc1                        42: ts6i 
 14: d9.PIN            29: icc2                        43: tsp 
 15: a1               

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
tspm                 ..........................................X....... 1
id10                 X.....X.......X...............XX.......X.X........ 7
id5                  .X.....X......X...............XX.......X.X........ 7
idhlatch             ..............X...........XXXX.X.......X.X........ 8
brst6                ........XX........................................ 2
brst                 ........XX......................XX.....X.......... 5
itr                  ........XX................XXXX.X........XX........ 9
id9                  .....X.......XX...............XX.......X.X........ 7
icc1                 ..........................XX............XX........ 4
id6                  ..X.......X...X...............XX.......X.X........ 7
id8                  ....X.......X.X...............XX.......X.X........ 7
id7                  ...X.......X..X...............XX.......X.X........ 7
idend                ........XX................XXXX.X.................. 7
ccs                  ...............XXXXX.............................. 5
g0                   ....................XXXXXX........XXXXX........... 11
icc2                 ..........................XXX...........XX........ 5
icc0                 ..........................XXXX..........XX........ 6
icc3                 ..........................XXXX..........XX........ 6
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB16 ***********************************
Number of function block inputs used/remaining:               43/11
Number of signals used by logic mapping into function block:  43
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB16_1        (b)     
ta6m                  1       0     0   4     FB16_2  91    I/O     I
b4d8                  2       0     0   3     FB16_3  92    I/O     I
b4d20                 2       0   \/1   2     FB16_4        (b)     (b)
g4                    6       1<-   0   0     FB16_5  93    I/O     O
g3                    6       1<-   0   0     FB16_6  94    I/O     O
b4d17                 2       0   /\1   2     FB16_7        (b)     (b)
g2                    6       1<-   0   0     FB16_8  95    I/O     O
b4d16                 2       0   /\1   2     FB16_9        (b)     (b)
b4d15                 2       0   \/1   2     FB16_10 96    I/O     I
g1                    6       1<-   0   0     FB16_11 97    I/O     O
b3d8                  3       0     0   2     FB16_12 98    I/O     I
b2d8                  3       0     0   2     FB16_13       (b)     (b)
b1d8                  3       0     0   2     FB16_14       (b)     (b)
b1d20                 3       0     0   2     FB16_15       (b)     (b)
b1d17                 3       0     0   2     FB16_16       (b)     (b)
b1d16                 3       0     0   2     FB16_17       (b)     (b)
b1d15                 3       0     0   2     FB16_18       (b)     (b)

Signals Used by Logic in Function Block
  1: d15.PIN           16: b2d8                        30: peot 
  2: d20.PIN           17: b3d8                        31: plx 
  3: d16.PIN           18: b4d15                       32: r0 
  4: d17.PIN           19: b4d16                       33: r1 
  5: ta6.PIN           20: b4d17                       34: r2 
  6: d8.PIN            21: b4d20                       35: r3 
  7: b1d15             22: b4d8                        36: r4 
  8: b1d16             23: brst                        37: rw 
  9: b1d17             24: g0                          38: shift 
 10: b1d20             25: g1                          39: tacc0 
 11: b1d8              26: g2                          40: tacc1 
 12: b2d15             27: g3                          41: tacc2 
 13: b2d16             28: g3_OBUF/g3_OBUF_SETF__$INT  42: tacc3 
 14: b2d17             29: g4                          43: tap 
 15: b2d20            

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
ta6m                 ..........................................X....... 1
b4d8                 ....XX...............XX......XX.....X.XXXX........ 11
b4d20                .X..X...............X.X......XX.....X.XXXX........ 11
g4                   .......................XXXXXX..XXXXX.............. 11
g3                   .......................XXXXXX..XXXXX.............. 11
b4d17                ...XX..............X..X......XX.....X.XXXX........ 11
g2                   .......................XXXXXX..XXXXX.............. 11
b4d16                ..X.X.............X...X......XX.....X.XXXX........ 11
b4d15                X...X............X....X......XX.....X.XXXX........ 11
g1                   .......................XXXXXX..XXXXX.............. 11
b3d8                 ....XX..........X....XX......XX.....XXXXXX........ 13
b2d8                 ....XX.........XX.....X......XX.....XXXXXX........ 13
b1d8                 ....XX....X....X......X.......X.....XXXXXX........ 12
b1d20                .X..X....X....X.......X.......X.....XXXXXX........ 12
b1d17                ...XX...X....X........X.......X.....XXXXXX........ 12
b1d16                ..X.X..X....X.........X.......X.....XXXXXX........ 12
b1d15                X...X.X....X..........X.......X.....XXXXXX........ 12
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

$OpTx$FX_DC$217 = ts6i
	# rcs
	# iack6 & !ieo
	# !tap & plx & brst;    

b1d0.D = rw & b2d0 & shift & plx & brst
	# rw & b1d0 & !shift & plx & brst
	# rw & !ta6.PIN & d0.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d0.CLK = clk;	// GCK    

b1d1.D = rw & b2d1 & shift & plx & brst
	# rw & b1d1 & !shift & plx & brst
	# rw & !ta6.PIN & d1.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d1.CLK = clk;	// GCK    

b1d10.D = rw & b2d10 & shift & plx & brst
	# rw & b1d10 & !shift & plx & brst
	# rw & !ta6.PIN & d10.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d10.CLK = clk;	// GCK    

b1d11.D = rw & b2d11 & shift & plx & brst
	# rw & b1d11 & !shift & plx & brst
	# rw & !ta6.PIN & d11.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d11.CLK = clk;	// GCK    

b1d12.D = rw & b2d12 & shift & plx & brst
	# rw & b1d12 & !shift & plx & brst
	# rw & !ta6.PIN & d12.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d12.CLK = clk;	// GCK    

b1d13.D = rw & b2d13 & shift & plx & brst
	# rw & b1d13 & !shift & plx & brst
	# rw & !ta6.PIN & d13.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d13.CLK = clk;	// GCK    

b1d14.D = rw & b2d14 & shift & plx & brst
	# rw & b1d14 & !shift & plx & brst
	# rw & !ta6.PIN & d14.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d14.CLK = clk;	// GCK    

b1d15.D = rw & b2d15 & shift & plx & brst
	# rw & b1d15 & !shift & plx & brst
	# rw & !ta6.PIN & d15.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d15.CLK = clk;	// GCK    

b1d16.D = rw & b2d16 & shift & plx & brst
	# rw & b1d16 & !shift & plx & brst
	# rw & !ta6.PIN & d16.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d16.CLK = clk;	// GCK    

b1d17.D = rw & b2d17 & shift & plx & brst
	# rw & b1d17 & !shift & plx & brst
	# rw & !ta6.PIN & d17.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d17.CLK = clk;	// GCK    

b1d18.D = rw & b2d18 & shift & plx & brst
	# rw & b1d18 & !shift & plx & brst
	# rw & !ta6.PIN & d18.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d18.CLK = clk;	// GCK    

b1d19.D = rw & b2d19 & shift & plx & brst
	# rw & b1d19 & !shift & plx & brst
	# rw & !ta6.PIN & d19.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d19.CLK = clk;	// GCK    

b1d2.D = rw & b2d2 & shift & plx & brst
	# rw & b1d2 & !shift & plx & brst
	# rw & !ta6.PIN & d2.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d2.CLK = clk;	// GCK    

b1d20.D = rw & b2d20 & shift & plx & brst
	# rw & b1d20 & !shift & plx & brst
	# rw & !ta6.PIN & d20.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d20.CLK = clk;	// GCK    

b1d21.D = rw & b2d21 & shift & plx & brst
	# rw & b1d21 & !shift & plx & brst
	# rw & !ta6.PIN & d21.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d21.CLK = clk;	// GCK    

b1d22.D = rw & b2d22 & shift & plx & brst
	# rw & b1d22 & !shift & plx & brst
	# rw & !ta6.PIN & d22.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d22.CLK = clk;	// GCK    

b1d23.D = rw & b2d23 & shift & plx & brst
	# rw & b1d23 & !shift & plx & brst
	# rw & !ta6.PIN & d23.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d23.CLK = clk;	// GCK    

b1d24.D = rw & b2d24 & shift & plx & brst
	# rw & b1d24 & !shift & plx & brst
	# rw & !ta6.PIN & d24.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d24.CLK = clk;	// GCK    

b1d25.D = rw & b2d25 & shift & plx & brst
	# rw & b1d25 & !shift & plx & brst
	# rw & !ta6.PIN & d25.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d25.CLK = clk;	// GCK    

b1d26.D = rw & b2d26 & shift & plx & brst
	# rw & b1d26 & !shift & plx & brst
	# rw & !ta6.PIN & d26.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d26.CLK = clk;	// GCK    

b1d27.D = rw & b2d27 & shift & plx & brst
	# rw & b1d27 & !shift & plx & brst
	# rw & !ta6.PIN & d27.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d27.CLK = clk;	// GCK    

b1d28.D = rw & b2d28 & shift & plx & brst
	# rw & b1d28 & !shift & plx & brst
	# rw & !ta6.PIN & d28.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d28.CLK = clk;	// GCK    

b1d29.D = rw & b2d29 & shift & plx & brst
	# rw & b1d29 & !shift & plx & brst
	# rw & !ta6.PIN & d29.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d29.CLK = clk;	// GCK    

b1d3.D = rw & b2d3 & shift & plx & brst
	# rw & b1d3 & !shift & plx & brst
	# rw & !ta6.PIN & d3.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d3.CLK = clk;	// GCK    

b1d30.D = rw & b2d30 & shift & plx & brst
	# rw & b1d30 & !shift & plx & brst
	# rw & !ta6.PIN & d30.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d30.CLK = clk;	// GCK    

b1d31.D = rw & b2d31 & shift & plx & brst
	# rw & b1d31 & !shift & plx & brst
	# rw & !ta6.PIN & d31.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d31.CLK = clk;	// GCK    

b1d4.D = rw & b2d4 & shift & plx & brst
	# rw & b1d4 & !shift & plx & brst
	# rw & !ta6.PIN & d4.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d4.CLK = clk;	// GCK    

b1d5.D = rw & b2d5 & shift & plx & brst
	# rw & b1d5 & !shift & plx & brst
	# rw & !ta6.PIN & d5.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d5.CLK = clk;	// GCK    

b1d6.D = rw & b2d6 & shift & plx & brst
	# rw & b1d6 & !shift & plx & brst
	# rw & !ta6.PIN & d6.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d6.CLK = clk;	// GCK    

b1d7.D = rw & b2d7 & shift & plx & brst
	# rw & b1d7 & !shift & plx & brst
	# rw & !ta6.PIN & d7.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d7.CLK = clk;	// GCK    

b1d8.D = rw & b2d8 & shift & plx & brst
	# rw & b1d8 & !shift & plx & brst
	# rw & !ta6.PIN & d8.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d8.CLK = clk;	// GCK    

b1d9.D = rw & b2d9 & shift & plx & brst
	# rw & b1d9 & !shift & plx & brst
	# rw & !ta6.PIN & d9.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & brst & !tacc0;
   b1d9.CLK = clk;	// GCK    

b2d0.D = b2d0 & !shift & plx & !peot & brst
	# rw & b3d0 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d0.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d0.CLK = clk;	// GCK    

b2d1.D = b2d1 & !shift & plx & !peot & brst
	# rw & b3d1 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d1.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d1.CLK = clk;	// GCK    

b2d10.D = b2d10 & !shift & plx & !peot & brst
	# rw & b3d10 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d10.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d10.CLK = clk;	// GCK    

b2d11.D = b2d11 & !shift & plx & !peot & brst
	# rw & b3d11 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d11.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d11.CLK = clk;	// GCK    

b2d12.D = b2d12 & !shift & plx & !peot & brst
	# rw & b3d12 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d12.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d12.CLK = clk;	// GCK    

b2d13.D = b2d13 & !shift & plx & !peot & brst
	# rw & b3d13 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d13.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d13.CLK = clk;	// GCK    

b2d14.D = b2d14 & !shift & plx & !peot & brst
	# rw & b3d14 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d14.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d14.CLK = clk;	// GCK    

b2d15.D = b2d15 & !shift & plx & !peot & brst
	# rw & b3d15 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d15.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d15.CLK = clk;	// GCK    

b2d16.D = b2d16 & !shift & plx & !peot & brst
	# rw & b3d16 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d16.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d16.CLK = clk;	// GCK    

b2d17.D = b2d17 & !shift & plx & !peot & brst
	# rw & b3d17 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d17.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d17.CLK = clk;	// GCK    

b2d18.D = b2d18 & !shift & plx & !peot & brst
	# rw & b3d18 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d18.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d18.CLK = clk;	// GCK    

b2d19.D = b2d19 & !shift & plx & !peot & brst
	# rw & b3d19 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d19.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d19.CLK = clk;	// GCK    

b2d2.D = b2d2 & !shift & plx & !peot & brst
	# rw & b3d2 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d2.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d2.CLK = clk;	// GCK    

b2d20.D = b2d20 & !shift & plx & !peot & brst
	# rw & b3d20 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d20.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d20.CLK = clk;	// GCK    

b2d21.D = b2d21 & !shift & plx & !peot & brst
	# rw & b3d21 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d21.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d21.CLK = clk;	// GCK    

b2d22.D = b2d22 & !shift & plx & !peot & brst
	# rw & b3d22 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d22.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d22.CLK = clk;	// GCK    

b2d23.D = b2d23 & !shift & plx & !peot & brst
	# rw & b3d23 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d23.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d23.CLK = clk;	// GCK    

b2d24.D = b2d24 & !shift & plx & !peot & brst
	# rw & b3d24 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d24.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d24.CLK = clk;	// GCK    

b2d25.D = b2d25 & !shift & plx & !peot & brst
	# rw & b3d25 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d25.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d25.CLK = clk;	// GCK    

b2d26.D = b2d26 & !shift & plx & !peot & brst
	# rw & b3d26 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d26.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d26.CLK = clk;	// GCK    

b2d27.D = b2d27 & !shift & plx & !peot & brst
	# rw & b3d27 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d27.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d27.CLK = clk;	// GCK    

b2d28.D = b2d28 & !shift & plx & !peot & brst
	# rw & b3d28 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d28.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d28.CLK = clk;	// GCK    

b2d29.D = b2d29 & !shift & plx & !peot & brst
	# rw & b3d29 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d29.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d29.CLK = clk;	// GCK    

b2d3.D = b2d3 & !shift & plx & !peot & brst
	# rw & b3d3 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d3.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d3.CLK = clk;	// GCK    

b2d30.D = b2d30 & !shift & plx & !peot & brst
	# rw & b3d30 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d30.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d30.CLK = clk;	// GCK    

b2d31.D = b2d31 & !shift & plx & !peot & brst
	# rw & b3d31 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d31.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d31.CLK = clk;	// GCK    

b2d4.D = b2d4 & !shift & plx & !peot & brst
	# rw & b3d4 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d4.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d4.CLK = clk;	// GCK    

b2d5.D = b2d5 & !shift & plx & !peot & brst
	# rw & b3d5 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d5.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d5.CLK = clk;	// GCK    

b2d6.D = b2d6 & !shift & plx & !peot & brst
	# rw & b3d6 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d6.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d6.CLK = clk;	// GCK    

b2d7.D = b2d7 & !shift & plx & !peot & brst
	# rw & b3d7 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d7.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d7.CLK = clk;	// GCK    

b2d8.D = b2d8 & !shift & plx & !peot & brst
	# rw & b3d8 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d8.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d8.CLK = clk;	// GCK    

b2d9.D = b2d9 & !shift & plx & !peot & brst
	# rw & b3d9 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d9.PIN & !tacc3 & !tacc2 & plx & 
	!tacc1 & !peot & brst & tacc0;
   b2d9.CLK = clk;	// GCK    

b3d0.D = b3d0 & !shift & plx & !peot & brst
	# rw & b4d0 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d0.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d0.CLK = clk;	// GCK    

b3d1.D = b3d1 & !shift & plx & !peot & brst
	# rw & b4d1 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d1.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d1.CLK = clk;	// GCK    

b3d10.D = b3d10 & !shift & plx & !peot & brst
	# rw & b4d10 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d10.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d10.CLK = clk;	// GCK    

b3d11.D = b3d11 & !shift & plx & !peot & brst
	# rw & b4d11 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d11.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d11.CLK = clk;	// GCK    

b3d12.D = b3d12 & !shift & plx & !peot & brst
	# rw & b4d12 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d12.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d12.CLK = clk;	// GCK    

b3d13.D = b3d13 & !shift & plx & !peot & brst
	# rw & b4d13 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d13.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d13.CLK = clk;	// GCK    

b3d14.D = b3d14 & !shift & plx & !peot & brst
	# rw & b4d14 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d14.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d14.CLK = clk;	// GCK    

b3d15.D = b3d15 & !shift & plx & !peot & brst
	# rw & b4d15 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d15.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d15.CLK = clk;	// GCK    

b3d16.D = b3d16 & !shift & plx & !peot & brst
	# rw & b4d16 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d16.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d16.CLK = clk;	// GCK    

b3d17.D = b3d17 & !shift & plx & !peot & brst
	# rw & b4d17 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d17.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d17.CLK = clk;	// GCK    

b3d18.D = b3d18 & !shift & plx & !peot & brst
	# rw & b4d18 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d18.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d18.CLK = clk;	// GCK    

b3d19.D = b3d19 & !shift & plx & !peot & brst
	# rw & b4d19 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d19.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d19.CLK = clk;	// GCK    

b3d2.D = b3d2 & !shift & plx & !peot & brst
	# rw & b4d2 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d2.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d2.CLK = clk;	// GCK    

b3d20.D = b3d20 & !shift & plx & !peot & brst
	# rw & b4d20 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d20.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d20.CLK = clk;	// GCK    

b3d21.D = b3d21 & !shift & plx & !peot & brst
	# rw & b4d21 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d21.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d21.CLK = clk;	// GCK    

b3d22.D = b3d22 & !shift & plx & !peot & brst
	# rw & b4d22 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d22.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d22.CLK = clk;	// GCK    

b3d23.D = b3d23 & !shift & plx & !peot & brst
	# rw & b4d23 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d23.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d23.CLK = clk;	// GCK    

b3d24.D = b3d24 & !shift & plx & !peot & brst
	# rw & b4d24 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d24.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d24.CLK = clk;	// GCK    

b3d25.D = b3d25 & !shift & plx & !peot & brst
	# rw & b4d25 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d25.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d25.CLK = clk;	// GCK    

b3d26.D = b3d26 & !shift & plx & !peot & brst
	# rw & b4d26 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d26.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d26.CLK = clk;	// GCK    

b3d27.D = b3d27 & !shift & plx & !peot & brst
	# rw & b4d27 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d27.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d27.CLK = clk;	// GCK    

b3d28.D = b3d28 & !shift & plx & !peot & brst
	# rw & b4d28 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d28.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d28.CLK = clk;	// GCK    

b3d29.D = b3d29 & !shift & plx & !peot & brst
	# rw & b4d29 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d29.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d29.CLK = clk;	// GCK    

b3d3.D = b3d3 & !shift & plx & !peot & brst
	# rw & b4d3 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d3.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d3.CLK = clk;	// GCK    

b3d30.D = b3d30 & !shift & plx & !peot & brst
	# rw & b4d30 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d30.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d30.CLK = clk;	// GCK    

b3d31.D = b3d31 & !shift & plx & !peot & brst
	# rw & b4d31 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d31.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d31.CLK = clk;	// GCK    

b3d4.D = b3d4 & !shift & plx & !peot & brst
	# rw & b4d4 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d4.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d4.CLK = clk;	// GCK    

b3d5.D = b3d5 & !shift & plx & !peot & brst
	# rw & b4d5 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d5.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d5.CLK = clk;	// GCK    

b3d6.D = b3d6 & !shift & plx & !peot & brst
	# rw & b4d6 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d6.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d6.CLK = clk;	// GCK    

b3d7.D = b3d7 & !shift & plx & !peot & brst
	# rw & b4d7 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d7.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d7.CLK = clk;	// GCK    

b3d8.D = b3d8 & !shift & plx & !peot & brst
	# rw & b4d8 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d8.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d8.CLK = clk;	// GCK    

b3d9.D = b3d9 & !shift & plx & !peot & brst
	# rw & b4d9 & shift & plx & !peot & brst
	# rw & !ta6.PIN & d9.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & !tacc0;
   b3d9.CLK = clk;	// GCK    

b4d0.D = b4d0 & plx & !peot & brst
	# rw & !ta6.PIN & d0.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d0.CLK = clk;	// GCK    

b4d1.D = b4d1 & plx & !peot & brst
	# rw & !ta6.PIN & d1.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d1.CLK = clk;	// GCK    

b4d10.D = b4d10 & plx & !peot & brst
	# rw & !ta6.PIN & d10.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d10.CLK = clk;	// GCK    

b4d11.D = b4d11 & plx & !peot & brst
	# rw & !ta6.PIN & d11.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d11.CLK = clk;	// GCK    

b4d12.D = b4d12 & plx & !peot & brst
	# rw & !ta6.PIN & d12.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d12.CLK = clk;	// GCK    

b4d13.D = b4d13 & plx & !peot & brst
	# rw & !ta6.PIN & d13.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d13.CLK = clk;	// GCK    

b4d14.D = b4d14 & plx & !peot & brst
	# rw & !ta6.PIN & d14.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d14.CLK = clk;	// GCK    

b4d15.D = b4d15 & plx & !peot & brst
	# rw & !ta6.PIN & d15.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d15.CLK = clk;	// GCK    

b4d16.D = b4d16 & plx & !peot & brst
	# rw & !ta6.PIN & d16.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d16.CLK = clk;	// GCK    

b4d17.D = b4d17 & plx & !peot & brst
	# rw & !ta6.PIN & d17.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d17.CLK = clk;	// GCK    

b4d18.D = b4d18 & plx & !peot & brst
	# rw & !ta6.PIN & d18.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d18.CLK = clk;	// GCK    

b4d19.D = b4d19 & plx & !peot & brst
	# rw & !ta6.PIN & d19.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d19.CLK = clk;	// GCK    

b4d2.D = b4d2 & plx & !peot & brst
	# rw & !ta6.PIN & d2.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d2.CLK = clk;	// GCK    

b4d20.D = b4d20 & plx & !peot & brst
	# rw & !ta6.PIN & d20.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d20.CLK = clk;	// GCK    

b4d21.D = b4d21 & plx & !peot & brst
	# rw & !ta6.PIN & d21.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d21.CLK = clk;	// GCK    

b4d22.D = b4d22 & plx & !peot & brst
	# rw & !ta6.PIN & d22.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d22.CLK = clk;	// GCK    

b4d23.D = b4d23 & plx & !peot & brst
	# rw & !ta6.PIN & d23.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d23.CLK = clk;	// GCK    

b4d24.D = b4d24 & plx & !peot & brst
	# rw & !ta6.PIN & d24.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d24.CLK = clk;	// GCK    

b4d25.D = b4d25 & plx & !peot & brst
	# rw & !ta6.PIN & d25.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d25.CLK = clk;	// GCK    

b4d26.D = b4d26 & plx & !peot & brst
	# rw & !ta6.PIN & d26.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d26.CLK = clk;	// GCK    

b4d27.D = b4d27 & plx & !peot & brst
	# rw & !ta6.PIN & d27.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d27.CLK = clk;	// GCK    

b4d28.D = b4d28 & plx & !peot & brst
	# rw & !ta6.PIN & d28.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d28.CLK = clk;	// GCK    

b4d29.D = b4d29 & plx & !peot & brst
	# rw & !ta6.PIN & d29.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d29.CLK = clk;	// GCK    

b4d3.D = b4d3 & plx & !peot & brst
	# rw & !ta6.PIN & d3.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d3.CLK = clk;	// GCK    

b4d30.D = b4d30 & plx & !peot & brst
	# rw & !ta6.PIN & d30.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d30.CLK = clk;	// GCK    

b4d31.D = b4d31 & plx & !peot & brst
	# rw & !ta6.PIN & d31.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d31.CLK = clk;	// GCK    

b4d4.D = b4d4 & plx & !peot & brst
	# rw & !ta6.PIN & d4.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d4.CLK = clk;	// GCK    

b4d5.D = b4d5 & plx & !peot & brst
	# rw & !ta6.PIN & d5.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d5.CLK = clk;	// GCK    

b4d6.D = b4d6 & plx & !peot & brst
	# rw & !ta6.PIN & d6.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d6.CLK = clk;	// GCK    

b4d7.D = b4d7 & plx & !peot & brst
	# rw & !ta6.PIN & d7.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d7.CLK = clk;	// GCK    

b4d8.D = b4d8 & plx & !peot & brst
	# rw & !ta6.PIN & d8.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d8.CLK = clk;	// GCK    

b4d9.D = b4d9 & plx & !peot & brst
	# rw & !ta6.PIN & d9.PIN & !tacc3 & !tacc2 & plx & 
	tacc1 & !peot & brst & tacc0;
   b4d9.CLK = clk;	// GCK    

bdip.D = bdip & !pci
	# bdip & tsp
	# bdip & !brst6
	# !tap.PIN & !tapcc0 & tapcc1;
   bdip.CLK = pclk;	// GCK
   !bdip.AP = rst;	// GSR
   bdip.OE = !plx;    

!bgplx.D = !brplx & !bg1;
   bgplx.CLK = clk;	// GCK    

!bgslt.D = brplx & !bg1 & !brslt;
   bgslt.CLK = clk;	// GCK    

bi = !plx;    

bmplx.T = !tsp.PIN & !bmplx & plx
	# !rw & !a5 & d22.PIN & !bs1.PIN & !bmplx & ts6c & 
	rcs
	# !rw & !a5 & !d22.PIN & tsp.PIN & !bs1.PIN & bmplx & 
	ts6c & rcs
	# !rw & !a5 & !d22.PIN & !bs1.PIN & bmplx & ts6c & 
	!plx & rcs;
   bmplx.CLK = clk;	// GCK
   !bmplx.AR = rst;	// GSR    

br60.D = stplx & brslt
	# brplx & brslt;
   br60.CLK = clk;	// GCK    

brst = rw & siz1.PIN & siz0.PIN & !plx & pci;    

brst6 = siz1.PIN & siz0.PIN;    

!bs0 = !a1 & plx & !a0;
   bs0.OE = plx;    

!bs1 = !a1 & plx & !tsiz1.PIN & !a0
	# !a1 & plx & tsiz1.PIN & !tsiz0.PIN & a0;
   bs1.OE = plx;    

!bs2 = a1 & plx & tsiz1.PIN & !tsiz0.PIN & !a0
	# a1 & plx & !tsiz1.PIN & tsiz0.PIN & !a0
	# !a1 & plx & !tsiz1.PIN & !tsiz0.PIN & !a0;
   bs2.OE = plx;    

!bs3 = a1 & plx & tsiz1.PIN & !tsiz0.PIN & a0
	# a1 & plx & !tsiz1.PIN & tsiz0.PIN & !a0
	# !a1 & plx & !tsiz1.PIN & !tsiz0.PIN & !a0;
   bs3.OE = plx;    

!burst = siz1.PIN & siz0.PIN & pci;
   burst.OE = !plx;    

!ccs = a31 & a30 & a29 & !a28 & a27;    

!cs0 = !a5 & !ide;    

!cs1 = a5 & !ide;    

!ct_irq = !inta & enbi1
	# !intb & enbi2
	# !intc & enbi3
	# !intd & enbi4;
   ct_irq.OE = ct_irq_xcBUF/ct_irq_xcBUF_TRST;    

ct_irq_xcBUF/ct_irq_xcBUF_TRST = !inta & enbi1
	# !intb & enbi2
	# !intc & enbi3
	# !intd & enbi4;    

d0.D = id0.PIN & ts6i
	# vect0 & iack6 & !ieo
	# rw & b1d0 & plx & brst;
   d0.CLK = clk;	// GCK
   d0.OE = rw & $OpTx$FX_DC$217;    

d1.D = id1.PIN & ts6i
	# iack6 & vect1 & !ieo
	# rw & b1d1 & plx & brst;
   d1.CLK = clk;	// GCK
   d1.OE = rw & $OpTx$FX_DC$217;    

d10.D = id10.PIN & ts6i
	# rw & b1d10 & plx & brst;
   d10.CLK = clk;	// GCK
   d10.OE = rw & $OpTx$FX_DC$217;    

d11.D = id11.PIN & ts6i
	# rw & b1d11 & plx & brst;
   d11.CLK = clk;	// GCK
   d11.OE = rw & $OpTx$FX_DC$217;    

d12.D = id12.PIN & ts6i
	# rw & b1d12 & plx & brst;
   d12.CLK = clk;	// GCK
   d12.OE = rw & $OpTx$FX_DC$217;    

d13.D = id13.PIN & ts6i
	# rw & b1d13 & plx & brst;
   d13.CLK = clk;	// GCK
   d13.OE = rw & $OpTx$FX_DC$217;    

d14.D = id14.PIN & ts6i
	# rw & b1d14 & plx & brst;
   d14.CLK = clk;	// GCK
   d14.OE = rw & $OpTx$FX_DC$217;    

d15.D = id15.PIN & ts6i
	# rw & b1d15 & plx & brst;
   d15.CLK = clk;	// GCK
   d15.OE = rw & $OpTx$FX_DC$217;    

d16.D = id0.PIN & idhlatch
	# rw & !a5 & enbi0 & ts6c
	# rw & d16 & ta6 & ts6i
	# rw & b1d16 & plx & brst;
   d16.CLK = clk;	// GCK
   d16.OE = rw & $OpTx$FX_DC$217;    

d17.D = id1.PIN & idhlatch
	# rw & !a5 & enbi1 & ts6c
	# rw & d17 & ta6 & ts6i
	# rw & b1d17 & plx & brst;
   d17.CLK = clk;	// GCK
   d17.OE = rw & $OpTx$FX_DC$217;    

d18.D = id2.PIN & idhlatch
	# rw & !a5 & enbi2 & ts6c
	# rw & d18 & ta6 & ts6i
	# rw & b1d18 & plx & brst;
   d18.CLK = clk;	// GCK
   d18.OE = rw & $OpTx$FX_DC$217;    

d19.D = id3.PIN & idhlatch
	# rw & !a5 & enbi3 & ts6c
	# rw & d19 & ta6 & ts6i
	# rw & b1d19 & plx & brst;
   d19.CLK = clk;	// GCK
   d19.OE = rw & $OpTx$FX_DC$217;    

d2.D = id2.PIN & ts6i
	# vect2 & iack6 & !ieo
	# rw & b1d2 & plx & brst;
   d2.CLK = clk;	// GCK
   d2.OE = rw & $OpTx$FX_DC$217;    

d20.D = id4.PIN & idhlatch
	# rw & !a5 & enbi4 & ts6c
	# rw & d20 & ta6 & ts6i
	# rw & b1d20 & plx & brst;
   d20.CLK = clk;	// GCK
   d20.OE = rw & $OpTx$FX_DC$217;    

d21.D = id5.PIN & idhlatch
	# rw & b1d21 & plx & brst
	# rw & ta6 & d21 & ts6i;
   d21.CLK = clk;	// GCK
   d21.OE = rw & $OpTx$FX_DC$217;    

d22.D = id6.PIN & idhlatch
	# rw & !a5 & bmplx & ts6c
	# rw & d22 & ta6 & ts6i
	# rw & b1d22 & plx & brst;
   d22.CLK = clk;	// GCK
   d22.OE = rw & $OpTx$FX_DC$217;    

d23.D = id7.PIN & idhlatch
	# rw & !a5 & stplx & ts6c
	# rw & d23 & ta6 & ts6i
	# rw & b1d23 & plx & brst;
   d23.CLK = clk;	// GCK
   d23.OE = rw & $OpTx$FX_DC$217;    

d24.D = id8.PIN & idhlatch
	# rw & b1d24 & plx & brst
	# rw & ta6 & d24 & ts6i;
   d24.CLK = clk;	// GCK
   d24.OE = rw & $OpTx$FX_DC$217;    

d25.D = id9.PIN & idhlatch
	# rw & !a5 & !inta & ts6c
	# rw & d25 & ta6 & ts6i
	# rw & b1d25 & plx & brst;
   d25.CLK = clk;	// GCK
   d25.OE = rw & $OpTx$FX_DC$217;    

d26.D = id10.PIN & idhlatch
	# rw & !a5 & !intb & ts6c
	# rw & d26 & ta6 & ts6i
	# rw & b1d26 & plx & brst;
   d26.CLK = clk;	// GCK
   d26.OE = rw & $OpTx$FX_DC$217;    

d27.D = id11.PIN & idhlatch
	# rw & !a5 & !intc & ts6c
	# rw & d27 & ta6 & ts6i
	# rw & b1d27 & plx & brst;
   d27.CLK = clk;	// GCK
   d27.OE = rw & $OpTx$FX_DC$217;    

d28.D = id12.PIN & idhlatch
	# rw & !a5 & !intd & ts6c
	# rw & d28 & ta6 & ts6i
	# rw & b1d28 & plx & brst;
   d28.CLK = clk;	// GCK
   d28.OE = rw & $OpTx$FX_DC$217;    

d29.D = id13.PIN & idhlatch
	# rw & b1d29 & plx & brst
	# rw & ta6 & d29 & ts6i;
   d29.CLK = clk;	// GCK
   d29.OE = rw & $OpTx$FX_DC$217;    

d3.D = id3.PIN & ts6i
	# vect3 & iack6 & !ieo
	# rw & b1d3 & plx & brst;
   d3.CLK = clk;	// GCK
   d3.OE = rw & $OpTx$FX_DC$217;    

d30.D = id14.PIN & idhlatch
	# rw & b1d30 & plx & brst
	# rw & ta6 & d30 & ts6i;
   d30.CLK = clk;	// GCK
   d30.OE = rw & $OpTx$FX_DC$217;    

d31.D = id15.PIN & idhlatch
	# rw & b1d31 & plx & brst
	# rw & ta6 & d31 & ts6i;
   d31.CLK = clk;	// GCK
   d31.OE = rw & $OpTx$FX_DC$217;    

d4.D = id4.PIN & ts6i
	# vect4 & iack6 & !ieo
	# rw & b1d4 & plx & brst;
   d4.CLK = clk;	// GCK
   d4.OE = rw & $OpTx$FX_DC$217;    

d5.D = id5.PIN & ts6i
	# vect5 & iack6 & !ieo
	# rw & b1d5 & plx & brst;
   d5.CLK = clk;	// GCK
   d5.OE = rw & $OpTx$FX_DC$217;    

d6.D = id6.PIN & ts6i
	# vect6 & iack6 & !ieo
	# rw & b1d6 & plx & brst;
   d6.CLK = clk;	// GCK
   d6.OE = rw & $OpTx$FX_DC$217;    

d7.D = id7.PIN & ts6i
	# vect7 & iack6 & !ieo
	# rw & b1d7 & plx & brst;
   d7.CLK = clk;	// GCK
   d7.OE = rw & $OpTx$FX_DC$217;    

d8.D = id8.PIN & ts6i
	# rw & b1d8 & plx & brst;
   d8.CLK = clk;	// GCK
   d8.OE = rw & $OpTx$FX_DC$217;    

d9.D = id9.PIN & ts6i
	# rw & b1d9 & plx & brst;
   d9.CLK = clk;	// GCK
   d9.OE = rw & $OpTx$FX_DC$217;    

enbi0.T = !rw & !a5 & d16.PIN & !bs1.PIN & !enbi0 & ts6c & 
	rcs
	# !rw & !a5 & !d16.PIN & !bs1.PIN & enbi0 & ts6c & 
	rcs;
   enbi0.CLK = clk;	// GCK
   !enbi0.AR = rst;	// GSR    

enbi1.T = !rw & !a5 & d17.PIN & !bs1.PIN & !enbi1 & ts6c & 
	rcs
	# !rw & !a5 & !d17.PIN & !bs1.PIN & enbi1 & ts6c & 
	rcs;
   enbi1.CLK = clk;	// GCK
   !enbi1.AR = rst;	// GSR    

enbi2.T = !rw & !a5 & d18.PIN & !bs1.PIN & !enbi2 & ts6c & 
	rcs
	# !rw & !a5 & !d18.PIN & !bs1.PIN & enbi2 & ts6c & 
	rcs;
   enbi2.CLK = clk;	// GCK
   !enbi2.AR = rst;	// GSR    

enbi3.T = !rw & !a5 & d19.PIN & !bs1.PIN & !enbi3 & ts6c & 
	rcs
	# !rw & !a5 & !d19.PIN & !bs1.PIN & enbi3 & ts6c & 
	rcs;
   enbi3.CLK = clk;	// GCK
   !enbi3.AR = rst;	// GSR    

enbi4.T = !rw & !a5 & d20.PIN & !bs1.PIN & !enbi4 & ts6c & 
	rcs
	# !rw & !a5 & !d20.PIN & !bs1.PIN & enbi4 & ts6c & 
	rcs;
   enbi4.CLK = clk;	// GCK
   !enbi4.AR = rst;	// GSR    

!g0.D = !r0 & !g0
	# !r0 & r4 & !g4
	# !r0 & r4 & r3 & !g3
	# r0 & r4 & r3 & r2 & r1
;Imported pterms FB15_14
	# r4 & r3 & r2 & r1 & !g1
;Imported pterms FB15_16
	# !r0 & r4 & r3 & r2 & !g2;
   g0.CLK = pciclk;	// GCK
   g0.AP = !g3_OBUF/g3_OBUF_SETF__$INT;    

!g1.D = !r1 & !g1
	# r0 & !r1 & !g0
	# r0 & r4 & !r1 & !g4
	# r0 & r4 & r3 & !r1 & !g3
;Imported pterms FB16_10
	# r0 & r4 & r3 & r2 & !r1 & !g2;
   g1.CLK = pciclk;	// GCK
   g1.AP = !g3_OBUF/g3_OBUF_SETF__$INT;    

!g2.D = !r2 & !g2
	# !r2 & r1 & !g1
	# r0 & !r2 & r1 & !g0
	# r0 & r4 & !r2 & r1 & !g4
;Imported pterms FB16_9
	# r0 & r4 & r3 & !r2 & r1 & !g3;
   g2.CLK = pciclk;	// GCK
   g2.AP = !g3_OBUF/g3_OBUF_SETF__$INT;    

!g3.D = !r3 & !g3
	# !r3 & r2 & !g2
	# !r3 & r2 & r1 & !g1
	# r0 & !r3 & r2 & r1 & !g0
;Imported pterms FB16_7
	# r0 & r4 & !r3 & r2 & r1 & !g4;
   g3.CLK = pciclk;	// GCK
   g3.AP = !g3_OBUF/g3_OBUF_SETF__$INT;    

g3_OBUF/g3_OBUF_SETF__$INT = rst & !prst;    

!g4.D = !r4 & !g4
	# !r4 & r3 & !g3
	# !r4 & r3 & r2 & !g2
	# !r4 & r3 & r2 & r1 & !g1
;Imported pterms FB16_4
	# r0 & !r4 & r3 & r2 & r1 & !g0;
   g4.CLK = pciclk;	// GCK
   g4.AP = !g3_OBUF/g3_OBUF_SETF__$INT;    

iack6 = tt1.PIN & !tm0.PIN & tt0.PIN & tm2.PIN & 
	tm1.PIN;    

icc0.D = ta6 & !icc0 & !icc3 & ts6i
	# ta6 & !icc0 & icc2 & ts6i
	# ta6 & !icc0 & ts6i & icc1;
   icc0.CLK = clk;	// GCK    

icc1.D = ta6 & icc0 & ts6i & !icc1
	# ta6 & !icc0 & ts6i & icc1;
   icc1.CLK = clk;	// GCK    

icc2.D = ta6 & !icc0 & icc2 & ts6i
	# ta6 & icc2 & ts6i & !icc1
	# ta6 & icc0 & !icc2 & ts6i & icc1;
   icc2.CLK = clk;	// GCK    

icc3.D = ta6 & icc0 & icc3 & !icc2 & ts6i
	# ta6 & !icc0 & icc3 & ts6i & icc1
	# ta6 & icc3 & icc2 & ts6i & !icc1
	# ta6 & icc0 & !icc3 & icc2 & ts6i & icc1;
   icc3.CLK = clk;	// GCK    

id0.D = !rw & d0.PIN & itr & !a1 & ts6i
	# !rw & d0.PIN & !itr & a1 & ts6i
	# !rw & d16.PIN & !itr & !a1 & ts6i;
   id0.CLK = clk;	// GCK
   id0.OE = !rw & !ide;    

id1.D = !rw & d1.PIN & itr & !a1 & ts6i
	# !rw & d1.PIN & !itr & a1 & ts6i
	# !rw & d17.PIN & !itr & !a1 & ts6i;
   id1.CLK = clk;	// GCK
   id1.OE = !rw & !ide;    

id10.D = !rw & d10.PIN & itr & !a1 & ts6i
	# !rw & d10.PIN & !itr & a1 & ts6i
	# !rw & d26.PIN & !itr & !a1 & ts6i;
   id10.CLK = clk;	// GCK
   id10.OE = !rw & !ide;    

id11.D = !rw & d11.PIN & itr & !a1 & ts6i
	# !rw & d11.PIN & !itr & a1 & ts6i
	# !rw & d27.PIN & !itr & !a1 & ts6i;
   id11.CLK = clk;	// GCK
   id11.OE = !rw & !ide;    

id12.D = !rw & d12.PIN & itr & !a1 & ts6i
	# !rw & d12.PIN & !itr & a1 & ts6i
	# !rw & d28.PIN & !itr & !a1 & ts6i;
   id12.CLK = clk;	// GCK
   id12.OE = !rw & !ide;    

id13.D = !rw & d13.PIN & itr & !a1 & ts6i
	# !rw & d13.PIN & !itr & a1 & ts6i
	# !rw & d29.PIN & !itr & !a1 & ts6i;
   id13.CLK = clk;	// GCK
   id13.OE = !rw & !ide;    

id14.D = !rw & d14.PIN & itr & !a1 & ts6i
	# !rw & d14.PIN & !itr & a1 & ts6i
	# !rw & d30.PIN & !itr & !a1 & ts6i;
   id14.CLK = clk;	// GCK
   id14.OE = !rw & !ide;    

id15.D = !rw & d15.PIN & itr & !a1 & ts6i
	# !rw & d15.PIN & !itr & a1 & ts6i
	# !rw & d31.PIN & !itr & !a1 & ts6i;
   id15.CLK = clk;	// GCK
   id15.OE = !rw & !ide;    

id2.D = !rw & d18.PIN & !itr & !a1 & ts6i
	# !rw & d2.PIN & itr & !a1 & ts6i
	# !rw & d2.PIN & !itr & a1 & ts6i;
   id2.CLK = clk;	// GCK
   id2.OE = !rw & !ide;    

id3.D = !rw & d19.PIN & !itr & !a1 & ts6i
	# !rw & d3.PIN & itr & !a1 & ts6i
	# !rw & d3.PIN & !itr & a1 & ts6i;
   id3.CLK = clk;	// GCK
   id3.OE = !rw & !ide;    

id4.D = !rw & d20.PIN & !itr & !a1 & ts6i
	# !rw & d4.PIN & itr & !a1 & ts6i
	# !rw & d4.PIN & !itr & a1 & ts6i;
   id4.CLK = clk;	// GCK
   id4.OE = !rw & !ide;    

id5.D = !rw & d21.PIN & !itr & !a1 & ts6i
	# !rw & d5.PIN & itr & !a1 & ts6i
	# !rw & d5.PIN & !itr & a1 & ts6i;
   id5.CLK = clk;	// GCK
   id5.OE = !rw & !ide;    

id6.D = !rw & d22.PIN & !itr & !a1 & ts6i
	# !rw & d6.PIN & itr & !a1 & ts6i
	# !rw & d6.PIN & !itr & a1 & ts6i;
   id6.CLK = clk;	// GCK
   id6.OE = !rw & !ide;    

id7.D = !rw & d23.PIN & !itr & !a1 & ts6i
	# !rw & d7.PIN & itr & !a1 & ts6i
	# !rw & d7.PIN & !itr & a1 & ts6i;
   id7.CLK = clk;	// GCK
   id7.OE = !rw & !ide;    

id8.D = !rw & d24.PIN & !itr & !a1 & ts6i
	# !rw & d8.PIN & itr & !a1 & ts6i
	# !rw & d8.PIN & !itr & a1 & ts6i;
   id8.CLK = clk;	// GCK
   id8.OE = !rw & !ide;    

id9.D = !rw & d25.PIN & !itr & !a1 & ts6i
	# !rw & d9.PIN & itr & !a1 & ts6i
	# !rw & d9.PIN & !itr & a1 & ts6i;
   id9.CLK = clk;	// GCK
   id9.OE = !rw & !ide;    

idend.D = siz1.PIN & !itr & !icc0 & !icc3 & icc2 & icc1
	# siz0.PIN & !itr & !icc0 & !icc3 & icc2 & icc1
	# !siz1.PIN & !siz0.PIN & itr & !icc0 & !icc3 & 
	icc2 & icc1;
   idend.CLK = clk;	// GCK    

idhlatch.D = rw & !itr & !a1 & !icc0 & !icc3 & icc2 & ts6i & 
	icc1;
   idhlatch.CLK = clk;	// GCK    

!ieo.D = !inta & enbi1
	# !intb & enbi2
	# !intc & enbi3
	# !intd & enbi4;
   ieo.CLK = clk;	// GCK    

ior.T = !ior & icc0 & !icc3 & icc2 & icc1
	# rw & ior & !icc0 & !icc3 & !icc2 & ts6i & !icc1;
   ior.CLK = clk;	// GCK    

iow.T = !iow & icc0 & !icc3 & icc2 & icc1
	# !rw & iow & !icc0 & !icc3 & !icc2 & ts6i & !icc1;
   iow.CLK = clk;	// GCK    

itr.D = ta6 & itr
	# ta6 & !siz1.PIN & !siz0.PIN & !icc0 & icc3 & 
	!icc2 & ts6i & !icc1;
   itr.CLK = clk;	// GCK    

!pcc0.T = !pcc0 & pcc2 & !pcc1;
   pcc0.CLK = pclk;	// GCK
   pcc0.CE = rw & plx & psync & brst;    

pcc1.T = pcc0;
   pcc1.CLK = pclk;	// GCK
   pcc1.CE = rw & plx & psync & brst;    

pcc2.T = pcc0 & pcc1
	# !pcc0 & pcc2 & !pcc1;
   pcc2.CLK = pclk;	// GCK
   pcc2.CE = rw & plx & psync & brst;    

pci = !a31 & a30
	# a30 & !a29
	# a31 & !a30 & !pcimap
	# a30 & !a28 & a27;    

pcimap.T = !rw & a5 & d2.PIN & !pcimap & ts6c & rcs
	# !rw & a5 & !d2.PIN & pcimap & ts6c & rcs;
   pcimap.CLK = clk;	// GCK
   !pcimap.AR = rst;	// GSR    

pcirst = rst & !prst;    

pclk.T = Vcc;
   pclk.CLK = clk;	// GCK    

peot.D = !pcc0 & pcc2 & plx & !pcc1 & brst;
   peot.CLK = clk;	// GCK    

plx.T = brplx & bg1 & bb & plx
	# !brplx & !bg1 & bb & !plx;
   plx.CLK = clk;	// GCK
   !plx.AR = rst;	// GSR    

prst.T = !rw & a5 & d0.PIN & !prst & ts6c & rcs
	# !rw & a5 & !d0.PIN & prst & ts6c & rcs;
   prst.CLK = clk;	// GCK
   !prst.AR = rst;	// GSR    

psync.T = rw & plx & !psync & taend & brst;
   psync.CLK = clk;	// GCK    

rcs = a31 & a30 & a29 & !a28 & !a27;    

shift.D = rw & pcc0 & !pcc2 & plx & brst
	# rw & !pcc2 & plx & pcc1 & brst;
   shift.CLK = pclk;	// GCK    

!siz0 = !tsiz1.PIN & !brst;
   siz0.OE = plx;    

!siz1 = !tsiz0.PIN & !brst;
   siz1.OE = plx;    

stplx.T = !rw & !a5 & d23.PIN & !bs1.PIN & !stplx & ts6c & 
	rcs
	# !rw & !a5 & !d23.PIN & !bs1.PIN & stplx & ts6c & 
	rcs;
   stplx.CLK = clk;	// GCK
   !stplx.AR = rst;	// GSR    

!ta6.D = ts6p & !tap.PIN & ta6
	# ta6 & idend & ts6i
	# ta6 & ts6c & rcs
	# ta6 & iack6 & !ieo & ts6bf;
   ta6.CLK = clk;	// GCK
   ta6.OE = !ta6_xcQ/ta6_xcQ_TRST__$INT;    

ta6_xcQ/ta6_xcQ_TRST__$INT = plx
	# !pci & !ts6i & !rcs & !iack6
	# !pci & !ts6i & !rcs & ieo;    

ta6cc0.T = Vcc;
   ta6cc0.CLK = clk;	// GCK
   ta6cc0.AR = !ts6p/ts6p_RSTF__$INT;
   ta6cc0.CE = ts6p & !ta6 & !plx & pci & brst6;    

ta6cc1.T = ta6cc0;
   ta6cc1.CLK = clk;	// GCK
   ta6cc1.AR = !ts6p/ts6p_RSTF__$INT;
   ta6cc1.CE = ts6p & !ta6 & !plx & pci & brst6;    

ta6m.D = !tap;
   ta6m.CLK = clk;	// GCK    

tacc0.D = !ta6.PIN & plx & brst & !tacc0;
   tacc0.CLK = clk;	// GCK    

tacc1.D = !ta6.PIN & plx & tacc1 & brst & !tacc0
	# !ta6.PIN & plx & !tacc1 & brst & tacc0;
   tacc1.CLK = clk;	// GCK    

tacc2.D = !ta6.PIN & tacc2 & plx & !tacc1 & brst
	# !ta6.PIN & tacc2 & plx & brst & !tacc0
	# !ta6.PIN & tacc3 & !tacc2 & plx & tacc1 & brst & 
	tacc0;
   tacc2.CLK = clk;	// GCK    

tacc3.D = !ta6.PIN & tacc3 & !tacc2 & plx & brst
	# !ta6.PIN & tacc3 & plx & !tacc1 & brst
	# !ta6.PIN & tacc3 & plx & brst & !tacc0
	# !ta6.PIN & !tacc3 & tacc2 & plx & tacc1 & brst & 
	tacc0;
   tacc3.CLK = clk;	// GCK    

taend.T = !tacc3 & !tacc2 & tacc1 & !taend & tacc0;
   taend.CLK = clk;	// GCK    

!tap.D = !tap & plx & brst
	# !tap & plx & !ta6m
	# !ta6.PIN & plx & !brst & !ta6m;
   tap.CLK = clk;	// GCK
   tap.OE = plx;    

tapcc0.T = Vcc;
   tapcc0.CLK = pclk;	// GCK
   !tapcc0.AR = rst;	// GSR
   tapcc0.CE = ts6p & !tap.PIN & !plx & pci & brst6;    

tapcc1.T = tapcc0;
   tapcc1.CLK = pclk;	// GCK
   !tapcc1.AR = rst;	// GSR
   tapcc1.CE = ts6p & !tap.PIN & !plx & pci & brst6;    

teap.D = teapm2
	# tea & teap;
   teap.CLK = clk;	// GCK    

teapm.D = !teap;
   teapm.CLK = clk;	// GCK    

teapm2.D = teapm;
   teapm2.CLK = clk;	// GCK    

tm0 = Vcc;
   tm0.OE = plx;    

tm1 = Gnd;
   tm1.OE = plx;    

tm2 = Vcc;
   tm2.OE = plx;    

!ts6.D = !tsp.PIN & plx & !tscnt;
   ts6.CLK = clk;	// GCK
   ts6.OE = plx;    

ts6bf.D = !ts6.PIN;
   ts6bf.CLK = clk;	// GCK    

ts6c.D = a31 & a30 & a29 & !a28 & !a27 & ts6bf;
   ts6c.CLK = clk;	// GCK    

ts6i.D = ta6 & ts6i
	# ta6 & !ide & ts6bf;
   ts6i.CLK = clk;	// GCK    

!ts6p.D = plx
	# !ts6p & !ts6bf
	# !ta6 & !brst6
	# !a31 & !a30 & !ts6p
;Imported pterms FB1_1
	# a31 & a30 & a29 & a28 & !ts6p
	# a31 & a30 & a29 & !a27 & !ts6p
;Imported pterms FB1_17
	# !ta6 & ta6cc0 & ta6cc1;
   ts6p.CLK = clk;	// GCK
   ts6p.AR = !ts6p/ts6p_RSTF__$INT;    

ts6p/ts6p_RSTF__$INT = rst & tea;    

tscnt.D = !tsp.PIN & plx
	# !tsp.PIN & tscnt;
   tscnt.CLK = clk;	// GCK    

tsiz0 = siz1.PIN & pci & !brst6;
   tsiz0.OE = !plx;    

tsiz1 = siz0.PIN & pci & !brst6;
   tsiz1.OE = !plx;    

!tsp.D = !tsp & !tspm
	# !plx & !ts6.PIN & !tspm;
   tsp.CLK = clk;	// GCK
   tsp.OE = !plx & !tsp;    

tspm.D = !tsp;
   tspm.CLK = clk;	// GCK    

tt0 = Gnd;
   tt0.OE = plx;    

tt1 = Gnd;
   tt1.OE = plx;    

ve4.T = !rw & !a5 & d4.PIN & !bs3.PIN & !ve4 & ts6c & 
	rcs
	# !rw & !a5 & !d4.PIN & !bs3.PIN & ve4 & ts6c & 
	rcs;
   ve4.CLK = clk;	// GCK
   !ve4.AR = rst;	// GSR    

ve5.T = !rw & !a5 & d5.PIN & !bs3.PIN & !ve5 & ts6c & 
	rcs
	# !rw & !a5 & !d5.PIN & !bs3.PIN & ve5 & ts6c & 
	rcs;
   ve5.CLK = clk;	// GCK
   !ve5.AR = rst;	// GSR    

ve6.T = !rw & !a5 & d6.PIN & !bs3.PIN & !ve6 & ts6c & 
	rcs
	# !rw & !a5 & !d6.PIN & !bs3.PIN & ve6 & ts6c & 
	rcs;
   ve6.CLK = clk;	// GCK
   !ve6.AR = rst;	// GSR    

ve7.T = !rw & !a5 & d7.PIN & !bs3.PIN & !ve7 & ts6c & 
	rcs
	# !rw & !a5 & !d7.PIN & !bs3.PIN & ve7 & ts6c & 
	rcs;
   ve7.CLK = clk;	// GCK
   !ve7.AR = rst;	// GSR    

vect0.D = inta & !intb & enbi2
	# inta & intb & intc & !intd & enbi4;
   vect0.CLK = clk;	// GCK    

vect1.D = !inta & enbi1
	# inta & !intb & enbi2;
   vect1.CLK = clk;	// GCK    

vect2.D = inta & intb & !intc & enbi3
	# inta & intb & intc & !intd & enbi4;
   vect2.CLK = clk;	// GCK    

vect3.D = !inta & enbi1
	# inta & !intb & enbi2
	# inta & intb & !intc & enbi3
	# inta & intb & intc & !intd & enbi4;
   vect3.CLK = clk;	// GCK    

vect4.D = !inta & enbi1 & ve4
	# inta & !intb & enbi2 & ve4
	# inta & intb & !intc & enbi3 & ve4
	# inta & intb & intc & !intd & enbi4 & ve4;
   vect4.CLK = clk;	// GCK    

vect5.D = !inta & enbi1 & ve5
	# inta & !intb & enbi2 & ve5
	# inta & intb & !intc & enbi3 & ve5
	# inta & intb & intc & !intd & enbi4 & ve5;
   vect5.CLK = clk;	// GCK    

vect6.D = !inta & enbi1 & ve6
	# inta & !intb & enbi2 & ve6
	# inta & intb & !intc & enbi3 & ve6
	# inta & intb & intc & !intd & enbi4 & ve6;
   vect6.CLK = clk;	// GCK    

vect7.D = !inta & enbi1 & ve7
	# inta & !intb & enbi2 & ve7
	# inta & intb & !intc & enbi3 & ve7
	# inta & intb & intc & !intd & enbi4 & ve7;
   vect7.CLK = clk;	// GCK    

******************************  Device Pin Out *****************************

Device : XC95288XL-7-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 VCC                              73 VCC                           
  2 d0                               74 id2                           
  3 d1                               75 id12                          
  4 d2                               76 id3                           
  5 d3                               77 id11                          
  6 d4                               78 id4                           
  7 bi                               79 id10                          
  8 VCC                              80 id5                           
  9 tap                              81 id9                           
 10 tsp                              82 id6                           
 11 burst                            83 id8                           
 12 KPR                              84 VCC                           
 13 ide                              85 id7                           
 14 ct_irq                           86 ccs                           
 15 bs3                              87 g0                            
 16 bs2                              88 r0                            
 17 bs1                              89 GND                           
 18 GND                              90 GND                           
 19 bs0                              91 r4                            
 20 tt1                              92 r3                            
 21 tt0                              93 g4                            
 22 tm2                              94 g3                            
 23 tm1                              95 g2                            
 24 tm0                              96 r2                            
 25 ieo                              97 g1                            
 26 br60                             98 r1                            
 27 brslt                            99 GND                           
 28 bg1                             100 pcirst                        
 29 GND                             101 inta                          
 30 clk                             102 intb                          
 31 bgslt                           103 intd                          
 32 pciclk                          104 intc                          
 33 ts6                             105 d31                           
 34 bb                              106 d30                           
 35 rw                              107 d29                           
 36 GND                             108 GND                           
 37 VCC                             109 VCC                           
 38 pclk                            110 d28                           
 39 tsiz1                           111 d27                           
 40 tsiz0                           112 d26                           
 41 siz1                            113 d25                           
 42 VCC                             114 GND                           
 43 bdip                            115 d24                           
 44 siz0                            116 d23                           
 45 tea                             117 d22                           
 46 ta6                             118 d21                           
 47 GND                             119 d20                           
 48 a31                             120 d19                           
 49 a30                             121 d18                           
 50 a29                             122 TDO                           
 51 a28                             123 GND                           
 52 a27                             124 d17                           
 53 a5                              125 d16                           
 54 a1                              126 d15                           
 55 VCC                             127 VCC                           
 56 a0                              128 KPR                           
 57 KPR                             129 d14                           
 58 cs1                             130 d13                           
 59 cs0                             131 d12                           
 60 KPR                             132 d11                           
 61 ior                             133 d10                           
 62 GND                             134 d9                            
 63 TDI                             135 teap                          
 64 iow                             136 bgplx                         
 65 TMS                             137 d8                            
 66 id15                            138 brplx                         
 67 TCK                             139 d7                            
 68 id0                             140 d6                            
 69 id14                            141 VCC                           
 70 id1                             142 d5                            
 71 id13                            143 rst                           
 72 GND                             144 GND                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95288xl-7-TQ144
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : ON
Exhaustive Fitting                          : ON
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25