cpldfit:  version J.36                              Xilinx Inc.
                                  Fitter Report
Design Name: CTPCI                               Date:  4-19-2010,  0:45AM
Device Used: XC95288XL-7-TQ144
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
277/288 ( 96%) 890 /1440 ( 62%) 711/864 ( 82%)   242/288 ( 84%) 115/117 ( 98%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          18/18*      36/54       31/90       7/ 8
FB2          18/18*      48/54       58/90       8/10
FB3          18/18*      40/54       43/90       2/ 5
FB4          13/18       51/54       67/90       6/ 6*
FB5          18/18*      36/54       42/90       6/ 8
FB6          17/18       51/54       64/90       5/ 8
FB7          18/18*      50/54       71/90       2/ 4
FB8          18/18*      45/54       58/90       5/ 5*
FB9          18/18*      32/54       27/90       2/ 9
FB10         18/18*      51/54       69/90       9/10
FB11         18/18*      46/54       60/90       6/ 7
FB12         13/18       51/54       63/90       6/ 6*
FB13         18/18*      43/54       60/90       6/ 6*
FB14         18/18*      44/54       54/90       4/ 8
FB15         18/18*      47/54       56/90       8/ 9
FB16         18/18*      40/54       67/90       4/ 8
             -----       -----       -----      -----    
            277/288     711/864     890/1440    86/117

* - Resource is exhausted

** Global Control Resources **

Signal 'ctclk' mapped onto global clock net GCK1.
Signal 'pciclk' mapped onto global clock net GCK2.
Signal 'pxclk' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Signal 'rst' mapped onto global set/reset net GSR.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   26          26    |  I/O              :   107     109
Output        :   24          24    |  GCK/IO           :     3       3
Bidirectional :   61          61    |  GTS/IO           :     4       4
GCK           :    3           3    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    1           1    |
                 ----        ----
        Total    115         115

** Power Data **

There are 277 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:265 - Logic for net 'ta6' exceeds physical capacity of device; the
   logic will be broken into intermediate nodes.
*************************  Summary of Mapped Logic  ************************

** 86 Outputs **

Signal                      Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                        Pts   Inps          No.  Type    Use     Mode Rate State
tt1                         1     2     FB1_5   20   I/O     I/O     STD  FAST 
tt0                         1     2     FB1_6   21   I/O     I/O     STD  FAST 
tm2                         1     2     FB1_8   22   I/O     I/O     STD  FAST 
tm1                         1     2     FB1_10  23   I/O     I/O     STD  FAST 
tm0                         1     2     FB1_12  24   I/O     I/O     STD  FAST 
ieo                         3     5     FB1_14  25   I/O     O       STD  FAST RESET
br60                        1     2     FB1_15  26   I/O     O       STD  FAST RESET
tap                         5     9     FB2_2   9    I/O     I/O     STD  FAST RESET
tsp                         3     4     FB2_3   10   I/O     I/O     STD  FAST RESET
burst                       2     4     FB2_5   11   I/O     O       STD  FAST 
i6                          6     11    FB2_10  14   I/O     O       STD  FAST 
bs0                         3     6     FB2_12  15   I/O     O       STD  FAST 
bs1                         3     6     FB2_14  16   I/O     O       STD  FAST 
bs2                         4     6     FB2_15  17   I/O     O       STD  FAST 
bs3                         4     6     FB2_17  19   I/O     O       STD  FAST 
bgslt                       1     4     FB3_12  31   I/O     O       STD  FAST RESET
ts6                         2     3     FB3_15  33   I/O     I/O     STD  FAST 
d0                          9     22    FB4_2   2    GTS/I/O I/O     STD  FAST RESET
d1                          9     22    FB4_5   3    GTS/I/O I/O     STD  FAST RESET
d2                          9     22    FB4_6   4    I/O     I/O     STD  FAST RESET
d3                          9     22    FB4_8   5    GTS/I/O I/O     STD  FAST RESET
d4                          9     22    FB4_12  6    GTS/I/O I/O     STD  FAST RESET
bi                          1     1     FB4_14  7    I/O     O       STD  FAST 
pxclk                       0     0     FB5_8   38   GCK/I/O GCK/O   STD  FAST RESET
tsiz1                       2     4     FB5_10  39   I/O     I/O     STD  FAST 
tsiz0                       2     4     FB5_12  40   I/O     I/O     STD  FAST 
siz1                        2     4     FB5_14  41   I/O     I/O     STD  FAST 
bdip                        5     8     FB5_15  43   I/O     O       STD  FAST RESET
siz0                        2     4     FB5_17  44   I/O     I/O     STD  FAST 
bgplx                       1     2     FB6_3   136  I/O     O       STD  FAST RESET
d8                          4     10    FB6_5   137  I/O     I/O     STD  FAST RESET
d7                          9     22    FB6_8   139  I/O     I/O     STD  FAST RESET
d6                          9     22    FB6_10  140  I/O     I/O     STD  FAST RESET
d5                          9     22    FB6_14  142  I/O     I/O     STD  FAST RESET
tea                         3     5     FB7_3   45   I/O     O       STD  FAST RESET
ta6                         13    28    FB7_5   46   I/O     I/O     STD  FAST RESET
d13                         4     10    FB8_2   130  I/O     I/O     STD  FAST RESET
d12                         4     10    FB8_3   131  I/O     I/O     STD  FAST RESET
d11                         4     10    FB8_5   132  I/O     I/O     STD  FAST RESET
d10                         4     10    FB8_8   133  I/O     I/O     STD  FAST RESET

Signal                      Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                        Pts   Inps          No.  Type    Use     Mode Rate State
d9                          4     10    FB8_10  134  I/O     I/O     STD  FAST RESET
cs1                         1     2     FB9_14  58   I/O     O       STD  FAST 
cs0                         1     2     FB9_17  59   I/O     O       STD  FAST 
d22                         5     13    FB10_2  117  I/O     I/O     STD  FAST RESET
d21                         5     13    FB10_3  118  I/O     I/O     STD  FAST RESET
d20                         5     14    FB10_5  119  I/O     I/O     STD  FAST RESET
d19                         5     14    FB10_6  120  I/O     I/O     STD  FAST RESET
d18                         5     14    FB10_8  121  I/O     I/O     STD  FAST RESET
d17                         5     14    FB10_10 124  I/O     I/O     STD  FAST RESET
d16                         5     14    FB10_11 125  I/O     I/O     STD  FAST RESET
d15                         4     10    FB10_12 126  I/O     I/O     STD  FAST RESET
d14                         4     10    FB10_17 129  I/O     I/O     STD  FAST RESET
ior                         4     8     FB11_5  61   I/O     O       STD  FAST RESET
iow                         4     8     FB11_10 64   I/O     O       STD  FAST RESET
id15                        4     8     FB11_11 66   I/O     I/O     STD  FAST RESET
id0                         4     8     FB11_12 68   I/O     I/O     STD  FAST RESET
id14                        4     8     FB11_14 69   I/O     I/O     STD  FAST RESET
id1                         4     8     FB11_17 70   I/O     I/O     STD  FAST RESET
d28                         5     14    FB12_2  110  I/O     I/O     STD  FAST RESET
d27                         5     14    FB12_3  111  I/O     I/O     STD  FAST RESET
d26                         5     14    FB12_5  112  I/O     I/O     STD  FAST RESET
d25                         5     14    FB12_8  113  I/O     I/O     STD  FAST RESET
d24                         5     14    FB12_10 115  I/O     I/O     STD  FAST RESET
d23                         5     13    FB12_12 116  I/O     I/O     STD  FAST RESET
id13                        4     8     FB13_2  71   I/O     I/O     STD  FAST RESET
id2                         4     8     FB13_8  74   I/O     I/O     STD  FAST RESET
id12                        4     8     FB13_11 75   I/O     I/O     STD  FAST RESET
id3                         4     8     FB13_14 76   I/O     I/O     STD  FAST RESET
id11                        4     8     FB13_15 77   I/O     I/O     STD  FAST RESET
id4                         4     8     FB13_17 78   I/O     I/O     STD  FAST RESET
pcirst                      1     2     FB14_3  100  I/O     O       STD  FAST 
d31                         5     13    FB14_11 105  I/O     I/O     STD  FAST RESET
d30                         5     13    FB14_14 106  I/O     I/O     STD  FAST RESET
d29                         5     13    FB14_15 107  I/O     I/O     STD  FAST RESET
id10                        4     8     FB15_2  79   I/O     I/O     STD  FAST RESET
id5                         4     8     FB15_3  80   I/O     I/O     STD  FAST RESET
id9                         4     8     FB15_8  81   I/O     I/O     STD  FAST RESET
id6                         4     8     FB15_10 82   I/O     I/O     STD  FAST RESET
id8                         4     8     FB15_11 83   I/O     I/O     STD  FAST RESET
id7                         4     8     FB15_12 85   I/O     I/O     STD  FAST RESET

Signal                      Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                        Pts   Inps          No.  Type    Use     Mode Rate State
ccs                         1     5     FB15_14 86   I/O     O       STD  FAST 
g0                          1     1     FB15_15 87   I/O     O       STD  FAST RESET
g4                          7     11    FB16_5  93   I/O     O       STD  FAST RESET
g3                          7     11    FB16_6  94   I/O     O       STD  FAST RESET
g2                          7     11    FB16_8  95   I/O     O       STD  FAST RESET
g1                          7     11    FB16_11 97   I/O     O       STD  FAST RESET

** 191 Buried Nodes **

Signal                      Total Total Loc     Pwr  Reg Init
Name                        Pts   Inps          Mode State
b4d9                        2     11    FB1_1   STD  RESET
b4d27                       2     11    FB1_2   STD  RESET
b4d23                       2     11    FB1_3   STD  RESET
b4d22                       2     11    FB1_4   STD  RESET
b4d21                       2     11    FB1_7   STD  RESET
b4d20                       2     11    FB1_9   STD  RESET
b4d2                        2     11    FB1_11  STD  RESET
b4d19                       2     11    FB1_13  STD  RESET
b4d17                       2     11    FB1_16  STD  RESET
b4d16                       2     11    FB1_17  STD  RESET
b4d15                       2     11    FB1_18  STD  RESET
b4d1                        2     11    FB2_1   STD  RESET
b4d0                        2     11    FB2_4   STD  RESET
b3d1                        3     13    FB2_6   STD  RESET
b3d0                        3     13    FB2_7   STD  RESET
b2d10                       3     13    FB2_8   STD  RESET
b2d1                        3     13    FB2_9   STD  RESET
b2d0                        3     13    FB2_11  STD  RESET
b1d10                       3     13    FB2_13  STD  RESET
b1d1                        3     13    FB2_16  STD  RESET
b1d0                        3     13    FB2_18  STD  RESET
b4d8                        2     11    FB3_1   STD  RESET
b4d28                       2     11    FB3_2   STD  RESET
b4d24                       2     11    FB3_3   STD  RESET
b4d18                       2     11    FB3_4   STD  RESET
b4d14                       2     11    FB3_5   STD  RESET
b4d13                       2     11    FB3_6   STD  RESET
b4d12                       2     11    FB3_7   STD  RESET
b4d10                       2     11    FB3_8   STD  RESET
b3d8                        3     13    FB3_9   STD  RESET
b3d28                       3     13    FB3_10  STD  RESET
b3d24                       3     13    FB3_11  STD  RESET
b3d18                       3     13    FB3_13  STD  RESET
b3d10                       3     13    FB3_14  STD  RESET
b2d28                       3     13    FB3_16  STD  RESET
b2d24                       3     13    FB3_17  STD  RESET
b2d18                       3     13    FB3_18  STD  RESET
ta6_xcQ/ta6_xcQ_TRST        7     14    FB4_1   STD  
psync                       1     5     FB4_10  STD  RESET
vect7                       2     6     FB4_11  STD  RESET

Signal                      Total Total Loc     Pwr  Reg Init
Name                        Pts   Inps          Mode State
vect6                       2     6     FB4_13  STD  RESET
vect5                       2     6     FB4_15  STD  RESET
vect4                       2     6     FB4_16  STD  RESET
iack6                       5     10    FB4_17  STD  
tapcc0                      1     5     FB5_1   STD  RESET
brst                        1     5     FB5_2   STD  
tapcc1                      2     6     FB5_3   STD  RESET
b4d26                       2     11    FB5_4   STD  RESET
b4d25                       2     11    FB5_5   STD  RESET
b3d26                       3     13    FB5_6   STD  RESET
b3d25                       3     13    FB5_7   STD  RESET
b2d26                       3     13    FB5_9   STD  RESET
b2d25                       3     13    FB5_11  STD  RESET
b1d28                       3     13    FB5_13  STD  RESET
b1d26                       3     13    FB5_16  STD  RESET
b1d25                       3     13    FB5_18  STD  RESET
tacc0                       1     4     FB6_2   STD  RESET
tacc1                       2     5     FB6_4   STD  RESET
b4d6                        2     11    FB6_6   STD  RESET
b4d5                        2     11    FB6_7   STD  RESET
tacc2                       3     7     FB6_9   STD  RESET
b3d6                        3     13    FB6_11  STD  RESET
b3d5                        3     13    FB6_12  STD  RESET
b2d6                        3     13    FB6_13  STD  RESET
b2d5                        3     13    FB6_15  STD  RESET
b1d6                        3     13    FB6_16  STD  RESET
b1d5                        3     13    FB6_17  STD  RESET
tacc3                       4     7     FB6_18  STD  RESET
ts6c                        1     6     FB7_1   STD  RESET
rcs                         1     5     FB7_2   STD  
ta6cc0                      2     7     FB7_4   STD  RESET
pci                         2     5     FB7_6   STD  
idhlatch                    2     9     FB7_7   STD  RESET
ta6cc1                      3     8     FB7_8   STD  RESET
itr                         3     9     FB7_9   STD  RESET
icc1                        3     4     FB7_10  STD  RESET
icc0                        3     7     FB7_11  STD  RESET
mski4                       4     11    FB7_12  STD  RESET
mski3                       4     11    FB7_13  STD  RESET
mski2                       4     11    FB7_14  STD  RESET

Signal                      Total Total Loc     Pwr  Reg Init
Name                        Pts   Inps          Mode State
idllatch                    4     10    FB7_15  STD  RESET
icc3                        5     7     FB7_16  STD  RESET
icc2                        5     7     FB7_17  STD  RESET
ts6p                        9     13    FB7_18  STD  RESET
b4d11                       2     11    FB8_1   STD  RESET
b3d9                        3     13    FB8_4   STD  RESET
b3d13                       3     13    FB8_6   STD  RESET
b3d12                       3     13    FB8_7   STD  RESET
b3d11                       3     13    FB8_9   STD  RESET
b2d9                        3     13    FB8_11  STD  RESET
b2d13                       3     13    FB8_12  STD  RESET
b2d12                       3     13    FB8_13  STD  RESET
b2d11                       3     13    FB8_14  STD  RESET
b1d9                        3     13    FB8_15  STD  RESET
b1d13                       3     13    FB8_16  STD  RESET
b1d12                       3     13    FB8_17  STD  RESET
b1d11                       3     13    FB8_18  STD  RESET
tspm2                       1     1     FB9_1   STD  RESET
tspm                        1     1     FB9_2   STD  RESET
ts6p/ts6p_RSTF__$INT        1     3     FB9_3   STD  
ts6bf                       1     1     FB9_4   STD  RESET
taend                       1     5     FB9_5   STD  RESET
peot                        1     6     FB9_6   STD  RESET
long                        1     2     FB9_7   STD  
brst6                       1     2     FB9_8   STD  
ts6i                        2     4     FB9_9   STD  RESET
shift                       2     7     FB9_10  STD  RESET
plx/plx_RSTF                2     3     FB9_11  STD  
pcc3                        2     7     FB9_12  STD  RESET
pcc1                        2     5     FB9_13  STD  RESET
pcc0                        2     8     FB9_15  STD  RESET
itf                         2     5     FB9_16  STD  RESET
pcc2                        3     8     FB9_18  STD  RESET
vect3                       1     5     FB10_1  STD  RESET
ta6m                        1     3     FB10_4  STD  RESET
vect2                       2     5     FB10_7  STD  RESET
vect1                       2     3     FB10_9  STD  RESET
d9_xcQ/d9_xcQ_TRST          2     5     FB10_13 STD  
vect0                       3     5     FB10_14 STD  RESET
d31_xcQ/d31_xcQ_TRST        3     8     FB10_15 STD  

Signal                      Total Total Loc     Pwr  Reg Init
Name                        Pts   Inps          Mode State
i6_xcBUF/i6_xcBUF_TRST      5     10    FB10_16 STD  
d7_xcQ/d7_xcQ_TRST          7     16    FB10_18 STD  
b3d17                       3     13    FB11_1  STD  RESET
b3d16                       3     13    FB11_2  STD  RESET
b3d15                       3     13    FB11_3  STD  RESET
b3d14                       3     13    FB11_4  STD  RESET
b2d17                       3     13    FB11_6  STD  RESET
b2d16                       3     13    FB11_7  STD  RESET
b2d15                       3     13    FB11_8  STD  RESET
b2d14                       3     13    FB11_9  STD  RESET
b1d17                       3     13    FB11_13 STD  RESET
b1d16                       3     13    FB11_15 STD  RESET
b1d15                       3     13    FB11_16 STD  RESET
b1d14                       3     13    FB11_18 STD  RESET
ve4                         6     11    FB12_1  STD  RESET
g0_OBUF/g0_OBUF_SETF__$INT  1     2     FB12_11 STD  
mski1                       4     11    FB12_13 STD  RESET
mski0                       4     11    FB12_14 STD  RESET
ve7                         6     11    FB12_15 STD  RESET
ve6                         6     11    FB12_17 STD  RESET
ve5                         6     11    FB12_18 STD  RESET
b3d27                       3     13    FB13_1  STD  RESET
b3d20                       3     13    FB13_3  STD  RESET
b3d2                        3     13    FB13_4  STD  RESET
b3d19                       3     13    FB13_5  STD  RESET
b2d27                       3     13    FB13_6  STD  RESET
b2d20                       3     13    FB13_7  STD  RESET
b2d2                        3     13    FB13_9  STD  RESET
b2d19                       3     13    FB13_10 STD  RESET
b1d27                       3     13    FB13_12 STD  RESET
b1d20                       3     13    FB13_13 STD  RESET
b1d2                        3     13    FB13_16 STD  RESET
b1d19                       3     13    FB13_18 STD  RESET
prst                        2     5     FB14_1  STD  RESET
b4d31                       2     11    FB14_2  STD  RESET
b4d30                       2     11    FB14_4  STD  RESET
b4d29                       2     11    FB14_5  STD  RESET
b3d31                       3     13    FB14_6  STD  RESET
b3d30                       3     13    FB14_7  STD  RESET
b3d29                       3     13    FB14_8  STD  RESET

Signal                      Total Total Loc     Pwr  Reg Init
Name                        Pts   Inps          Mode State
b2d31                       3     13    FB14_9  STD  RESET
b2d30                       3     13    FB14_10 STD  RESET
b2d29                       3     13    FB14_12 STD  RESET
b1d31                       3     13    FB14_13 STD  RESET
b1d30                       3     13    FB14_16 STD  RESET
b1d29                       3     13    FB14_17 STD  RESET
b1d18                       3     13    FB14_18 STD  RESET
b3d23                       3     13    FB15_1  STD  RESET
b3d22                       3     13    FB15_4  STD  RESET
b3d21                       3     13    FB15_5  STD  RESET
b2d23                       3     13    FB15_6  STD  RESET
b2d22                       3     13    FB15_7  STD  RESET
b2d21                       3     13    FB15_9  STD  RESET
b1d24                       3     13    FB15_13 STD  RESET
b1d23                       3     13    FB15_16 STD  RESET
b1d22                       3     13    FB15_17 STD  RESET
b1d21                       3     13    FB15_18 STD  RESET
b4d7                        2     11    FB16_1  STD  RESET
b4d4                        2     11    FB16_2  STD  RESET
b4d3                        2     11    FB16_3  STD  RESET
b3d7                        3     13    FB16_4  STD  RESET
b3d4                        3     13    FB16_7  STD  RESET
b3d3                        3     13    FB16_9  STD  RESET
b2d8                        3     13    FB16_10 STD  RESET
b2d7                        3     13    FB16_12 STD  RESET
b2d4                        3     13    FB16_13 STD  RESET
b2d3                        3     13    FB16_14 STD  RESET
b1d8                        3     13    FB16_15 STD  RESET
b1d7                        3     13    FB16_16 STD  RESET
b1d4                        3     13    FB16_17 STD  RESET
b1d3                        3     13    FB16_18 STD  RESET

** 29 Inputs **

Signal                      Loc     Pin  Pin     Pin     
Name                                No.  Type    Use     
brslt                       FB1_17  27   I/O     I
retry                       FB2_6   12   I/O     I
ide                         FB2_8   13   I/O     I
bg60                        FB3_2   28   I/O     I
ctclk                       FB3_10  30   GCK/I/O GCK
pciclk                      FB3_14  32   GCK/I/O GCK
bb                          FB5_2   34   I/O     I
rw                          FB5_5   35   I/O     I
teap                        FB6_2   135  I/O     I
brplx                       FB6_6   138  I/O     I
rst                         FB6_15  143  GSR/I/O GSR/I
a31                         FB7_12  48   I/O     I
a30                         FB7_15  49   I/O     I
a29                         FB9_2   50   I/O     I
a28                         FB9_3   51   I/O     I
a27                         FB9_5   52   I/O     I
a5                          FB9_6   53   I/O     I
a1                          FB9_8   54   I/O     I
a0                          FB9_11  56   I/O     I
lint                        FB10_14 128  I/O     I
inta                        FB14_5  101  I/O     I
intb                        FB14_6  102  I/O     I
intd                        FB14_8  103  I/O     I
intc                        FB14_10 104  I/O     I
r0                          FB15_17 88   I/O     I
r4                          FB16_2  91   I/O     I
r3                          FB16_3  92   I/O     I
r2                          FB16_10 96   I/O     I
r1                          FB16_12 98   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               36/18
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d9                  2       0     0   3     FB1_1         (b)     (b)
b4d27                 2       0     0   3     FB1_2         (b)     (b)
b4d23                 2       0     0   3     FB1_3         (b)     (b)
b4d22                 2       0     0   3     FB1_4         (b)     (b)
tt1                   1       0     0   4     FB1_5   20    I/O     I/O
tt0                   1       0     0   4     FB1_6   21    I/O     I/O
b4d21                 2       0     0   3     FB1_7         (b)     (b)
tm2                   1       0     0   4     FB1_8   22    I/O     I/O
b4d20                 2       0     0   3     FB1_9         (b)     (b)
tm1                   1       0     0   4     FB1_10  23    I/O     I/O
b4d2                  2       0     0   3     FB1_11        (b)     (b)
tm0                   1       0     0   4     FB1_12  24    I/O     I/O
b4d19                 2       0     0   3     FB1_13        (b)     (b)
ieo                   3       0     0   2     FB1_14  25    I/O     O
br60                  1       0     0   4     FB1_15  26    I/O     O
b4d17                 2       0     0   3     FB1_16        (b)     (b)
b4d16                 2       0     0   3     FB1_17  27    I/O     I
b4d15                 2       0     0   3     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d2.PIN            13: b4d15             25: bg60 
  2: d15.PIN           14: b4d16             26: brplx 
  3: d20.PIN           15: b4d17             27: brslt 
  4: d16.PIN           16: b4d19             28: brst 
  5: d21.PIN           17: b4d2              29: ieo 
  6: d17.PIN           18: b4d20             30: peot 
  7: d22.PIN           19: b4d21             31: plx/plx_RSTF 
  8: d23.PIN           20: b4d22             32: rw 
  9: d19.PIN           21: b4d23             33: tacc0 
 10: d27.PIN           22: b4d27             34: tacc1 
 11: ta6.PIN           23: b4d9              35: tacc2 
 12: d9.PIN            24: bb                36: tacc3 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
b4d9                 ..........XX..........X....XXX.XXXXX.... 11
b4d27                .........XX..........X.....XXX.XXXXX.... 11
b4d23                .......X..X.........X......XXX.XXXXX.... 11
b4d22                ......X...X........X.......XXX.XXXXX.... 11
tt1                  .......................X....X........... 2
tt0                  .......................X....X........... 2
b4d21                ....X.....X.......X........XXX.XXXXX.... 11
tm2                  .......................X....X........... 2
b4d20                ..X.......X......X.........XXX.XXXXX.... 11
tm1                  .......................X....X........... 2
b4d2                 X.........X.....X..........XXX.XXXXX.... 11
tm0                  .......................X....X........... 2
b4d19                ........X.X....X...........XXX.XXXXX.... 11
ieo                  .......................XXX..X.X......... 5
br60                 .........................XX............. 2
b4d17                .....X....X...X............XXX.XXXXX.... 11
b4d16                ...X......X..X.............XXX.XXXXX.... 11
b4d15                .X........X.X..............XXX.XXXXX.... 11
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               48/6
Number of signals used by logic mapping into function block:  48
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d1                  2       0     0   3     FB2_1         (b)     (b)
tap                   5       0     0   0     FB2_2   9     I/O     I/O
tsp                   3       0     0   2     FB2_3   10    I/O     I/O
b4d0                  2       0     0   3     FB2_4         (b)     (b)
burst                 2       0     0   3     FB2_5   11    I/O     O
b3d1                  3       0     0   2     FB2_6   12    I/O     I
b3d0                  3       0     0   2     FB2_7         (b)     (b)
b2d10                 3       0     0   2     FB2_8   13    I/O     I
b2d1                  3       0   \/1   1     FB2_9         (b)     (b)
i6                    6       1<-   0   0     FB2_10  14    I/O     O
b2d0                  3       0     0   2     FB2_11        (b)     (b)
bs0                   3       0     0   2     FB2_12  15    I/O     O
b1d10                 3       0     0   2     FB2_13        (b)     (b)
bs1                   3       0     0   2     FB2_14  16    I/O     O
bs2                   4       0     0   1     FB2_15  17    I/O     O
b1d1                  3       0     0   2     FB2_16        (b)     (b)
bs3                   4       0     0   1     FB2_17  19    I/O     O
b1d0                  3       0     0   2     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d0.PIN            17: b2d10                   33: mski1 
  2: d1.PIN            18: b3d0                    34: mski2 
  3: ts6.PIN           19: b3d1                    35: mski3 
  4: d10.PIN           20: b3d10                   36: mski4 
  5: siz0.PIN          21: b4d0                    37: pci 
  6: siz1.PIN          22: b4d1                    38: peot 
  7: tsiz0.PIN         23: bb                      39: rw 
  8: tsiz1.PIN         24: brst                    40: shift 
  9: ta6.PIN           25: i6_xcBUF/i6_xcBUF_TRST  41: ta6m 
 10: a0                26: ieo                     42: tacc0 
 11: a1                27: inta                    43: tacc1 
 12: b1d0              28: intb                    44: tacc2 
 13: b1d1              29: intc                    45: tacc3 
 14: b1d10             30: intd                    46: tap 
 15: b2d0              31: lint                    47: tsp 
 16: b2d1              32: mski0                   48: tspm2 

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b4d1                 .X......X............X.X.X...........XX..XXXX..... 11
tap                  ........X..............X.X..............XXXXXX.... 9
tsp                  ..X......................X....................XX.. 4
b4d0                 X.......X...........X..X.X...........XX..XXXX..... 11
burst                ....XX...................X..........X............. 4
b3d1                 .X......X.........X..X.X.X...........XXX.XXXX..... 13
b3d0                 X.......X........X..X..X.X...........XXX.XXXX..... 13
b2d10                ...X....X.......X..X...X.X...........XXX.XXXX..... 13
b2d1                 .X......X......X..X....X.X...........XXX.XXXX..... 13
i6                   ........................X.XXXXXXXXXX.............. 11
b2d0                 X.......X.....X..X.....X.X...........XXX.XXXX..... 13
bs0                  ......XX.XX...........X..X........................ 6
b1d10                ...X....X....X..X......X.X...........XXX.XXXX..... 13
bs1                  ......XX.XX...........X..X........................ 6
bs2                  ......XX.XX...........X..X........................ 6
b1d1                 .X......X...X..X.......X.X...........XXX.XXXX..... 13
bs3                  ......XX.XX...........X..X........................ 6
b1d0                 X.......X..X..X........X.X...........XXX.XXXX..... 13
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               40/14
Number of signals used by logic mapping into function block:  40
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d8                  2       0     0   3     FB3_1         (b)     (b)
b4d28                 2       0     0   3     FB3_2   28    I/O     I
b4d24                 2       0     0   3     FB3_3         (b)     (b)
b4d18                 2       0     0   3     FB3_4         (b)     (b)
b4d14                 2       0     0   3     FB3_5         (b)     (b)
b4d13                 2       0     0   3     FB3_6         (b)     (b)
b4d12                 2       0     0   3     FB3_7         (b)     (b)
b4d10                 2       0     0   3     FB3_8         (b)     (b)
b3d8                  3       0     0   2     FB3_9         (b)     (b)
b3d28                 3       0     0   2     FB3_10  30    GCK/I/O GCK
b3d24                 3       0     0   2     FB3_11        (b)     (b)
bgslt                 1       0     0   4     FB3_12  31    I/O     O
b3d18                 3       0     0   2     FB3_13        (b)     (b)
b3d10                 3       0     0   2     FB3_14  32    GCK/I/O GCK
ts6                   2       0     0   3     FB3_15  33    I/O     I/O
b2d28                 3       0     0   2     FB3_16        (b)     (b)
b2d24                 3       0     0   2     FB3_17        (b)     (b)
b2d18                 3       0     0   2     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d10.PIN           15: b3d24             28: bgplx 
  2: d12.PIN           16: b3d28             29: brplx 
  3: d13.PIN           17: b3d8              30: brslt 
  4: d14.PIN           18: b4d10             31: brst 
  5: d18.PIN           19: b4d12             32: ieo 
  6: d24.PIN           20: b4d13             33: peot 
  7: d28.PIN           21: b4d14             34: rw 
  8: ta6.PIN           22: b4d18             35: shift 
  9: d8.PIN            23: b4d24             36: tacc0 
 10: b2d18             24: b4d28             37: tacc1 
 11: b2d24             25: b4d8              38: tacc2 
 12: b2d28             26: bb                39: tacc3 
 13: b3d10             27: bg60              40: tsp.PIN 
 14: b3d18            

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b4d8                 .......XX...............X.....XXXX.XXXX........... 11
b4d28                ......XX...............X......XXXX.XXXX........... 11
b4d24                .....X.X..............X.......XXXX.XXXX........... 11
b4d18                ....X..X.............X........XXXX.XXXX........... 11
b4d14                ...X...X............X.........XXXX.XXXX........... 11
b4d13                ..X....X...........X..........XXXX.XXXX........... 11
b4d12                .X.....X..........X...........XXXX.XXXX........... 11
b4d10                X......X.........X............XXXX.XXXX........... 11
b3d8                 .......XX.......X.......X.....XXXXXXXXX........... 13
b3d28                ......XX.......X.......X......XXXXXXXXX........... 13
b3d24                .....X.X......X.......X.......XXXXXXXXX........... 13
bgslt                ..........................XXXX.................... 4
b3d18                ....X..X.....X.......X........XXXXXXXXX........... 13
b3d10                X......X....X....X............XXXXXXXXX........... 13
ts6                  .........................X.....X.......X.......... 3
b2d28                ......XX...X...X..............XXXXXXXXX........... 13
b2d24                .....X.X..X...X...............XXXXXXXXX........... 13
b2d18                ....X..X.X...X................XXXXXXXXX........... 13
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               51/3
Number of signals used by logic mapping into function block:  51
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
ta6_xcQ/ta6_xcQ_TRST
                      7       2<-   0   0     FB4_1         (b)     (b)
d0                    9       4<-   0   0     FB4_2   2     GTS/I/O I/O
(unused)              0       0   /\4   1     FB4_3         (b)     (b)
(unused)              0       0   \/4   1     FB4_4         (b)     (b)
d1                    9       4<-   0   0     FB4_5   3     GTS/I/O I/O
d2                    9       4<-   0   0     FB4_6   4     I/O     I/O
(unused)              0       0   /\4   1     FB4_7         (b)     (b)
d3                    9       4<-   0   0     FB4_8   5     GTS/I/O I/O
(unused)              0       0   /\4   1     FB4_9         (b)     (b)
psync                 1       0     0   4     FB4_10        (b)     (b)
vect7                 2       0   \/2   1     FB4_11        (b)     (b)
d4                    9       4<-   0   0     FB4_12  6     GTS/I/O I/O
vect6                 2       0   /\2   1     FB4_13        (b)     (b)
bi                    1       0     0   4     FB4_14  7     I/O     O
vect5                 2       0     0   3     FB4_15        (b)     (b)
vect4                 2       0     0   3     FB4_16        (b)     (b)
iack6                 5       0     0   0     FB4_17        (b)     (b)
(unused)              0       0   \/2   3     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: tm0.PIN           18: d1                  35: mski3 
  2: tm1.PIN           19: d2                  36: mski4 
  3: tm2.PIN           20: d3                  37: pci 
  4: tt0.PIN           21: d4                  38: psync 
  5: tt1.PIN           22: d7_xcQ/d7_xcQ_TRST  39: rcs 
  6: id0.PIN           23: iack6               40: rw 
  7: id1.PIN           24: ide                 41: ta6 
  8: id2.PIN           25: idllatch            42: taend 
  9: id3.PIN           26: ieo                 43: ve4 
 10: id4.PIN           27: inta                44: ve5 
 11: b1d0              28: intb                45: ve6 
 12: b1d1              29: intc                46: ve7 
 13: b1d2              30: intd                47: vect0 
 14: b1d3              31: lint                48: vect1 
 15: b1d4              32: mski0               49: vect2 
 16: brst              33: mski1               50: vect3 
 17: d0                34: mski2               51: vect4 

Signal                        1         2         3         4         5         6 FB
Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
ta6_xcQ/ta6_xcQ_TRST 
                     ......................X..XXXXXXXXXXXX.X..................... 14
d0                   .....X....X....XX....XXXXXXXXXXXXXXX...XX.....X............. 22
d1                   ......X....X...X.X...XXXXXXXXXXXXXXX...XX......X............ 22
d2                   .......X....X..X..X..XXXXXXXXXXXXXXX...XX.......X........... 22
d3                   ........X....X.X...X.XXXXXXXXXXXXXXX...XX........X.......... 22
psync                ...............X.........X...........X.X.X.................. 5
vect7                ..........................XXXXX..............X.............. 6
d4                   .........X....XX....XXXXXXXXXXXXXXXX...XX.........X......... 22
vect6                ..........................XXXXX.............X............... 6
bi                   .........................X.................................. 1
vect5                ..........................XXXXX............X................ 6
vect4                ..........................XXXXX...........X................. 6
iack6                XXXXX..........................XXXXX........................ 10
                    0----+----1----+----2----+----3----+----4----+----5----+----6
                              0         0         0         0         0         0
*********************************** FB5  ***********************************
Number of function block inputs used/remaining:               36/18
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
tapcc0                1       0     0   4     FB5_1         (b)     (b)
brst                  1       0     0   4     FB5_2   34    I/O     I
tapcc1                2       0     0   3     FB5_3         (b)     (b)
b4d26                 2       0     0   3     FB5_4         (b)     (b)
b4d25                 2       0     0   3     FB5_5   35    I/O     I
b3d26                 3       0     0   2     FB5_6         (b)     (b)
b3d25                 3       0     0   2     FB5_7         (b)     (b)
pxclk                 0       0     0   5     FB5_8   38    GCK/I/O GCK/O
b2d26                 3       0     0   2     FB5_9         (b)     (b)
tsiz1                 2       0     0   3     FB5_10  39    I/O     I/O
b2d25                 3       0     0   2     FB5_11        (b)     (b)
tsiz0                 2       0     0   3     FB5_12  40    I/O     I/O
b1d28                 3       0     0   2     FB5_13        (b)     (b)
siz1                  2       0     0   3     FB5_14  41    I/O     I/O
bdip                  5       0     0   0     FB5_15  43    I/O     O
b1d26                 3       0     0   2     FB5_16        (b)     (b)
siz0                  2       0     0   3     FB5_17  44    I/O     I/O
b1d25                 3       0     0   2     FB5_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d25.PIN           13: b2d25             25: pci 
  2: d26.PIN           14: b2d26             26: peot 
  3: d28.PIN           15: b2d28             27: rw 
  4: siz0.PIN          16: b3d25             28: shift 
  5: siz1.PIN          17: b3d26             29: tacc0 
  6: tsiz0.PIN         18: b4d25             30: tacc1 
  7: tsiz1.PIN         19: b4d26             31: tacc2 
  8: ta6.PIN           20: bb                32: tacc3 
  9: tap.PIN           21: bdip              33: tapcc0 
 10: b1d25             22: brst              34: tapcc1 
 11: b1d26             23: brst6             35: ts6p 
 12: b1d28             24: ieo               36: tsp 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
tapcc0               ........X.............XXX.........X..... 5
brst                 ...XX..................XX.X............. 5
tapcc1               ........X.............XXX.......X.X..... 6
b4d26                .X.....X..........X..X.X.XX.XXXX........ 11
b4d25                X......X.........X...X.X.XX.XXXX........ 11
b3d26                .X.....X........X.X..X.X.XXXXXXX........ 13
b3d25                X......X.......X.X...X.X.XXXXXXX........ 13
pxclk                ........................................ 0
b2d26                .X.....X.....X..X....X.X.XXXXXXX........ 13
tsiz1                ...X..................XXX............... 4
b2d25                X......X....X..X.....X.X.XXXXXXX........ 13
tsiz0                ....X.................XXX............... 4
b1d28                ..X....X...X..X......X.X.XXXXXXX........ 13
siz1                 .....X.............X.X.X................ 4
bdip                 ........X...........X.XXX.......XX.X.... 8
b1d26                .X.....X..X..X.......X.X.XXXXXXX........ 13
siz0                 ......X............X.X.X................ 4
b1d25                X......X.X..X........X.X.XXXXXXX........ 13
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB6  ***********************************
Number of function block inputs used/remaining:               51/3
Number of signals used by logic mapping into function block:  51
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB6_1         (b)     
tacc0                 1       0     0   4     FB6_2   135   I/O     I
bgplx                 1       0     0   4     FB6_3   136   I/O     O
tacc1                 2       0     0   3     FB6_4         (b)     (b)
d8                    4       0     0   1     FB6_5   137   I/O     I/O
b4d6                  2       0     0   3     FB6_6   138   I/O     I
b4d5                  2       0   \/2   1     FB6_7         (b)     (b)
d7                    9       4<-   0   0     FB6_8   139   I/O     I/O
tacc2                 3       0   /\2   0     FB6_9         (b)     (b)
d6                    9       4<-   0   0     FB6_10  140   I/O     I/O
b3d6                  3       2<- /\4   0     FB6_11        (b)     (b)
b3d5                  3       0   /\2   0     FB6_12        (b)     (b)
b2d6                  3       0   \/2   0     FB6_13        (b)     (b)
d5                    9       4<-   0   0     FB6_14  142   I/O     I/O
b2d5                  3       0   /\2   0     FB6_15  143   GSR/I/O GSR/I
b1d6                  3       0     0   2     FB6_16        (b)     (b)
b1d5                  3       0     0   2     FB6_17        (b)     (b)
tacc3                 4       0     0   1     FB6_18        (b)     (b)

Signals Used by Logic in Function Block
  1: id5.PIN           18: bg60                35: lint 
  2: id6.PIN           19: brplx               36: mski0 
  3: id7.PIN           20: brst                37: mski1 
  4: id8.PIN           21: d5                  38: mski2 
  5: d5.PIN            22: d6                  39: mski3 
  6: ta6.PIN           23: d7                  40: mski4 
  7: d6.PIN            24: d7_xcQ/d7_xcQ_TRST  41: peot 
  8: b1d5              25: d8                  42: rw 
  9: b1d6              26: d9_xcQ/d9_xcQ_TRST  43: shift 
 10: b1d7              27: iack6               44: ta6 
 11: b1d8              28: ide                 45: tacc0 
 12: b2d5              29: idllatch            46: tacc1 
 13: b2d6              30: ieo                 47: tacc2 
 14: b3d5              31: inta                48: tacc3 
 15: b3d6              32: intb                49: vect5 
 16: b4d5              33: intc                50: vect6 
 17: b4d6              34: intd                51: vect7 

Signal                        1         2         3         4         5         6 FB
Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
tacc0                .....X.............X.........X..............X............... 4
bgplx                .................XX......................................... 2
tacc1                .....X.............X.........X..............XX.............. 5
d8                   ...X......X........X....XX.XXX...........X.X................ 10
b4d6                 .....XX.........X..X.........X..........XX..XXXX............ 11
b4d5                 ....XX.........X...X.........X..........XX..XXXX............ 11
d7                   ..X......X.........X..XX..XXXXXXXXXXXXXX.X.X......X......... 22
tacc2                .....X.............X.........X..............XXXX............ 7
d6                   .X......X..........X.X.X..XXXXXXXXXXXXXX.X.X.....X.......... 22
b3d6                 .....XX.......X.X..X.........X..........XXX.XXXX............ 13
b3d5                 ....XX.......X.X...X.........X..........XXX.XXXX............ 13
b2d6                 .....XX.....X.X....X.........X..........XXX.XXXX............ 13
d5                   X......X...........XX..X..XXXXXXXXXXXXXX.X.X....X........... 22
b2d5                 ....XX.....X.X.....X.........X..........XXX.XXXX............ 13
b1d6                 .....XX.X...X......X.........X..........XXX.XXXX............ 13
b1d5                 ....XX.X...X.......X.........X..........XXX.XXXX............ 13
tacc3                .....X.............X.........X..............XXXX............ 7
                    0----+----1----+----2----+----3----+----4----+----5----+----6
                              0         0         0         0         0         0
*********************************** FB7  ***********************************
Number of function block inputs used/remaining:               50/4
Number of signals used by logic mapping into function block:  50
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
ts6c                  1       0   /\4   0     FB7_1         (b)     (b)
rcs                   1       0     0   4     FB7_2         (b)     (b)
tea                   3       0     0   2     FB7_3   45    I/O     O
ta6cc0                2       0   \/3   0     FB7_4         (b)     (b)
ta6                  13       8<-   0   0     FB7_5   46    I/O     I/O
pci                   2       2<- /\5   0     FB7_6         (b)     (b)
idhlatch              2       0   /\2   1     FB7_7         (b)     (b)
ta6cc1                3       0     0   2     FB7_8         (b)     (b)
itr                   3       0     0   2     FB7_9         (b)     (b)
icc1                  3       0     0   2     FB7_10        (b)     (b)
icc0                  3       0     0   2     FB7_11        (b)     (b)
mski4                 4       0     0   1     FB7_12  48    I/O     I
mski3                 4       0     0   1     FB7_13        (b)     (b)
mski2                 4       0     0   1     FB7_14        (b)     (b)
idllatch              4       0     0   1     FB7_15  49    I/O     I
icc3                  5       0     0   0     FB7_16        (b)     (b)
icc2                  5       0     0   0     FB7_17        (b)     (b)
ts6p                  9       4<-   0   0     FB7_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d20.PIN           18: icc0              35: mski4 
  2: d18.PIN           19: icc1              36: pci 
  3: d19.PIN           20: icc2              37: rcs 
  4: tsiz0.PIN         21: icc3              38: retry 
  5: tsiz1.PIN         22: ieo               39: rw 
  6: ta6.PIN           23: inta              40: ta6 
  7: tap.PIN           24: intb              41: ta6_xcQ/ta6_xcQ_TRST 
  8: a0                25: intc              42: ta6cc0 
  9: a1                26: intd              43: ta6cc1 
 10: a27               27: itf               44: tea 
 11: a28               28: itr               45: teap 
 12: a29               29: lint              46: ts6bf 
 13: a30               30: long              47: ts6c 
 14: a31               31: mski0             48: ts6i 
 15: a5                32: mski1             49: ts6p 
 16: brst6             33: mski2             50: ts6p/ts6p_RSTF__$INT 
 17: iack6             34: mski3            

Signal                        1         2         3         4         5         6 FB
Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
ts6c                 .........XXXXX...............................X.............. 6
rcs                  .........XXXXX.............................................. 5
tea                  .....................X.............X.X......X...X........... 5
ta6cc0               ...............X.....X.............X...X.X.X....X........... 7
ta6                  ......X.........XXXXX.XXXXXXXXXXXXX.XX.XX...XXXXX........... 28
pci                  .........XXXXX.............................................. 5
idhlatch             ........X........XXXX.....XX..........X........X............ 9
ta6cc1               ...............X.....X.............X...X.XXX....X........... 8
itr                  .....X...........XXXX.....XX.X.................X............ 9
icc1                 .................XX....................X.......X............ 4
icc0                 .................XXXX.....X............X.......X............ 7
mski4                X..XX..XX.....X......X............X.X.X.......X............. 11
mski3                ..XXX..XX.....X......X...........X..X.X.......X............. 11
mski2                .X.XX..XX.....X......X..........X...X.X.......X............. 11
idllatch             ........X........XXXX.....XX.X........X........X............ 10
icc3                 .................XXXX.....X............X.......X............ 7
icc2                 .................XXXX.....X............X.......X............ 7
ts6p                 .........XXXXX.X.....X.................X.XX..X..XX.......... 13
                    0----+----1----+----2----+----3----+----4----+----5----+----6
                              0         0         0         0         0         0
*********************************** FB8  ***********************************
Number of function block inputs used/remaining:               45/9
Number of signals used by logic mapping into function block:  45
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d11                 2       0     0   3     FB8_1         (b)     (b)
d13                   4       0     0   1     FB8_2   130   I/O     I/O
d12                   4       0     0   1     FB8_3   131   I/O     I/O
b3d9                  3       0     0   2     FB8_4         (b)     (b)
d11                   4       0     0   1     FB8_5   132   I/O     I/O
b3d13                 3       0     0   2     FB8_6         (b)     (b)
b3d12                 3       0     0   2     FB8_7         (b)     (b)
d10                   4       0     0   1     FB8_8   133   I/O     I/O
b3d11                 3       0     0   2     FB8_9         (b)     (b)
d9                    4       0     0   1     FB8_10  134   I/O     I/O
b2d9                  3       0     0   2     FB8_11        (b)     (b)
b2d13                 3       0     0   2     FB8_12        (b)     (b)
b2d12                 3       0     0   2     FB8_13        (b)     (b)
b2d11                 3       0     0   2     FB8_14        (b)     (b)
b1d9                  3       0     0   2     FB8_15        (b)     (b)
b1d13                 3       0     0   2     FB8_16        (b)     (b)
b1d12                 3       0     0   2     FB8_17        (b)     (b)
b1d11                 3       0     0   2     FB8_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d11.PIN           16: b2d11             31: d12 
  2: d12.PIN           17: b2d12             32: d13 
  3: d13.PIN           18: b2d13             33: d9 
  4: id9.PIN           19: b2d9              34: d9_xcQ/d9_xcQ_TRST 
  5: id10.PIN          20: b3d11             35: ide 
  6: id11.PIN          21: b3d12             36: idllatch 
  7: id12.PIN          22: b3d13             37: ieo 
  8: id13.PIN          23: b3d9              38: peot 
  9: ta6.PIN           24: b4d11             39: rw 
 10: d9.PIN            25: b4d12             40: shift 
 11: b1d10             26: b4d13             41: ta6 
 12: b1d11             27: b4d9              42: tacc0 
 13: b1d12             28: brst              43: tacc1 
 14: b1d13             29: d10               44: tacc2 
 15: b1d9              30: d11               45: tacc3 

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b4d11                X.......X..............X...X........XXX..XXXX..... 11
d13                  .......X.....X.............X...X.XXXX.X.X......... 10
d12                  ......X.....X..............X..X..XXXX.X.X......... 10
b3d9                 ........XX............X...XX........XXXX.XXXX..... 13
d11                  .....X.....X...............X.X...XXXX.X.X......... 10
b3d13                ..X.....X............X...X.X........XXXX.XXXX..... 13
b3d12                .X......X...........X...X..X........XXXX.XXXX..... 13
d10                  ....X.....X................XX....XXXX.X.X......... 10
b3d11                X.......X..........X...X...X........XXXX.XXXX..... 13
d9                   ...X..........X............X....XXXXX.X.X......... 10
b2d9                 ........XX........X...X....X........XXXX.XXXX..... 13
b2d13                ..X.....X........X...X.....X........XXXX.XXXX..... 13
b2d12                .X......X.......X...X......X........XXXX.XXXX..... 13
b2d11                X.......X......X...X.......X........XXXX.XXXX..... 13
b1d9                 ........XX....X...X........X........XXXX.XXXX..... 13
b1d13                ..X.....X....X...X.........X........XXXX.XXXX..... 13
b1d12                .X......X...X...X..........X........XXXX.XXXX..... 13
b1d11                X.......X..X...X...........X........XXXX.XXXX..... 13
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB9  ***********************************
Number of function block inputs used/remaining:               32/22
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
tspm2                 1       0     0   4     FB9_1         (b)     (b)
tspm                  1       0     0   4     FB9_2   50    I/O     I
ts6p/ts6p_RSTF__$INT
                      1       0     0   4     FB9_3   51    I/O     I
ts6bf                 1       0     0   4     FB9_4         (b)     (b)
taend                 1       0     0   4     FB9_5   52    I/O     I
peot                  1       0     0   4     FB9_6   53    I/O     I
long                  1       0     0   4     FB9_7         (b)     (b)
brst6                 1       0     0   4     FB9_8   54    I/O     I
ts6i                  2       0     0   3     FB9_9         (b)     (b)
shift                 2       0     0   3     FB9_10        (b)     (b)
plx/plx_RSTF          2       0     0   3     FB9_11  56    I/O     I
pcc3                  2       0     0   3     FB9_12  57    I/O     (b)
pcc1                  2       0     0   3     FB9_13        (b)     (b)
cs1                   1       0     0   4     FB9_14  58    I/O     O
pcc0                  2       0     0   3     FB9_15        (b)     (b)
itf                   2       0     0   3     FB9_16        (b)     (b)
cs0                   1       0     0   4     FB9_17  59    I/O     O
pcc2                  3       0     0   2     FB9_18        (b)     (b)

Signals Used by Logic in Function Block
  1: d1.PIN            12: pcc0              23: tacc1 
  2: ts6.PIN           13: pcc1              24: tacc2 
  3: siz0.PIN          14: pcc2              25: tacc3 
  4: siz1.PIN          15: pcc3              26: taend 
  5: a5                16: prst              27: tea 
  6: bb                17: psync             28: ts6bf 
  7: bg60              18: rcs               29: ts6c 
  8: brst              19: rst               30: ts6i 
  9: ide               20: rw                31: tsp 
 10: ieo               21: ta6               32: tspm 
 11: itf               22: tacc0            

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
tspm2                ...............................X........ 1
tspm                 ..............................X......... 1
ts6p/ts6p_RSTF__$INT 
                     ...............X..X.......X............. 3
ts6bf                .X...................................... 1
taend                .....................XXXXX.............. 5
peot                 .......X.X.XXXX......................... 6
long                 ..XX.................................... 2
brst6                ..XX.................................... 2
ts6i                 ........X...........X......X.X.......... 4
shift                .......X.X.XXXX....X.................... 7
plx/plx_RSTF         .....XX...........X..................... 3
pcc3                 .......X.X.XXX..X..X.................... 7
pcc1                 .......X.X.X....X..X.................... 5
cs1                  ....X........................X.......... 2
pcc0                 .......X.X.XXXX.X..X.................... 8
itf                  X...X.....X......X..........X........... 5
cs0                  ....X........................X.......... 2
pcc2                 .......X.X.XXXX.X..X.................... 8
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB10 ***********************************
Number of function block inputs used/remaining:               51/3
Number of signals used by logic mapping into function block:  51
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
vect3                 1       0   /\1   3     FB10_1        (b)     (b)
d22                   5       0     0   0     FB10_2  117   I/O     I/O
d21                   5       0     0   0     FB10_3  118   I/O     I/O
ta6m                  1       0     0   4     FB10_4        (b)     (b)
d20                   5       0     0   0     FB10_5  119   I/O     I/O
d19                   5       0     0   0     FB10_6  120   I/O     I/O
vect2                 2       0     0   3     FB10_7        (b)     (b)
d18                   5       0     0   0     FB10_8  121   I/O     I/O
vect1                 2       0     0   3     FB10_9        (b)     (b)
d17                   5       0     0   0     FB10_10 124   I/O     I/O
d16                   5       0     0   0     FB10_11 125   I/O     I/O
d15                   4       0     0   1     FB10_12 126   I/O     I/O
d9_xcQ/d9_xcQ_TRST    2       0     0   3     FB10_13       (b)     (b)
vect0                 3       0     0   2     FB10_14 128   I/O     I
d31_xcQ/d31_xcQ_TRST
                      3       0     0   2     FB10_15       (b)     (b)
i6_xcBUF/i6_xcBUF_TRST
                      5       0     0   0     FB10_16       (b)     (b)
d14                   4       0   \/1   0     FB10_17 129   I/O     I/O
d7_xcQ/d7_xcQ_TRST    7       2<-   0   0     FB10_18       (b)     (b)

Signals Used by Logic in Function Block
  1: id0.PIN           18: b1d21                 35: idllatch 
  2: id1.PIN           19: b1d22                 36: ieo 
  3: id2.PIN           20: brst                  37: inta 
  4: id3.PIN           21: d14                   38: intb 
  5: id4.PIN           22: d15                   39: intc 
  6: id5.PIN           23: d16                   40: intd 
  7: id6.PIN           24: d17                   41: lint 
  8: id14.PIN          25: d18                   42: mski0 
  9: id15.PIN          26: d19                   43: mski1 
 10: a5                27: d20                   44: mski2 
 11: b1d14             28: d21                   45: mski3 
 12: b1d15             29: d22                   46: mski4 
 13: b1d16             30: d31_xcQ/d31_xcQ_TRST  47: rcs 
 14: b1d17             31: d9_xcQ/d9_xcQ_TRST    48: rw 
 15: b1d18             32: iack6                 49: ta6 
 16: b1d19             33: ide                   50: tap 
 17: b1d20             34: idhlatch              51: ts6c 

Signal                        1         2         3         4         5         6 FB
Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
vect3                ....................................XXXXX................... 5
d22                  ......X..X........XX........XX..XX.X..........XXX.X......... 13
d21                  .....X...X.......X.X.......X.X..XX.X..........XXX.X......... 13
ta6m                 ...................X...............X.............X.......... 3
d20                  ....X....X......X..X......X..X..XX.X.........XXXX.X......... 14
d19                  ...X.....X.....X...X.....X...X..XX.X........X.XXX.X......... 14
vect2                ....................................XXXXX................... 5
d18                  ..X......X....X....X....X....X..XX.X.......X..XXX.X......... 14
vect1                ....................................XX..X................... 3
d17                  .X.......X...X.....X...X.....X..XX.X......X...XXX.X......... 14
d16                  X........X..X......X..X......X..XX.X.....X....XXX.X......... 14
d15                  ........X..X.......X.X........X.X.XX...........XX........... 10
d9_xcQ/d9_xcQ_TRST   ...................X............X..X...........X.X.......... 5
vect0                ....................................XXXXX................... 5
d31_xcQ/d31_xcQ_TRST 
                     .........X.........X............X..X..........XX.XX......... 8
i6_xcBUF/i6_xcBUF_TRST 
                     ....................................XXXXXXXXXX.............. 10
d14                  .......X..X........XX.........X.X.XX...........XX........... 10
d7_xcQ/d7_xcQ_TRST   ...................X...........XX..XXXXXXXXXXX.X.X.......... 16
                    0----+----1----+----2----+----3----+----4----+----5----+----6
                              0         0         0         0         0         0
*********************************** FB11 ***********************************
Number of function block inputs used/remaining:               46/8
Number of signals used by logic mapping into function block:  46
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b3d17                 3       0     0   2     FB11_1        (b)     (b)
b3d16                 3       0     0   2     FB11_2        (b)     (b)
b3d15                 3       0     0   2     FB11_3  60    I/O     (b)
b3d14                 3       0     0   2     FB11_4        (b)     (b)
ior                   4       0     0   1     FB11_5  61    I/O     O
b2d17                 3       0     0   2     FB11_6        (b)     (b)
b2d16                 3       0     0   2     FB11_7        (b)     (b)
b2d15                 3       0     0   2     FB11_8        (b)     (b)
b2d14                 3       0     0   2     FB11_9        (b)     (b)
iow                   4       0     0   1     FB11_10 64    I/O     O
id15                  4       0     0   1     FB11_11 66    I/O     I/O
id0                   4       0     0   1     FB11_12 68    I/O     I/O
b1d17                 3       0     0   2     FB11_13       (b)     (b)
id14                  4       0     0   1     FB11_14 69    I/O     I/O
b1d16                 3       0     0   2     FB11_15       (b)     (b)
b1d15                 3       0     0   2     FB11_16       (b)     (b)
id1                   4       0     0   1     FB11_17 70    I/O     I/O
b1d14                 3       0     0   2     FB11_18       (b)     (b)

Signals Used by Logic in Function Block
  1: d0.PIN            17: b2d16             32: ide 
  2: d1.PIN            18: b2d17             33: ieo 
  3: d14.PIN           19: b3d14             34: ior 
  4: d15.PIN           20: b3d15             35: iow 
  5: d16.PIN           21: b3d16             36: itf 
  6: d17.PIN           22: b3d17             37: itr 
  7: d30.PIN           23: b4d14             38: long 
  8: d31.PIN           24: b4d15             39: peot 
  9: ta6.PIN           25: b4d16             40: rw 
 10: a1                26: b4d17             41: shift 
 11: b1d14             27: brst              42: tacc0 
 12: b1d15             28: icc0              43: tacc1 
 13: b1d16             29: icc1              44: tacc2 
 14: b1d17             30: icc2              45: tacc3 
 15: b2d14             31: icc3              46: ts6i 
 16: b2d15            

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b3d17                .....X..X............X...XX.....X.....XXXXXXX..... 13
b3d16                ....X...X...........X...X.X.....X.....XXXXXXX..... 13
b3d15                ...X....X..........X...X..X.....X.....XXXXXXX..... 13
b3d14                ..X.....X.........X...X...X.....X.....XXXXXXX..... 13
ior                  ...........................XXXX..X.X...X.....X.... 8
b2d17                .....X..X........X...X....X.....X.....XXXXXXX..... 13
b2d16                ....X...X.......X...X.....X.....X.....XXXXXXX..... 13
b2d15                ...X....X......X...X......X.....X.....XXXXXXX..... 13
b2d14                ..X.....X.....X...X.......X.....X.....XXXXXXX..... 13
iow                  ...........................XXXX...XX...X.....X.... 8
id15                 ...X...X.X.....................X....XX.X.....X.... 8
id0                  X...X....X.....................X....XX.X.....X.... 8
b1d17                .....X..X....X...X........X.....X.....XXXXXXX..... 13
id14                 ..X...X..X.....................X....XX.X.....X.... 8
b1d16                ....X...X...X...X.........X.....X.....XXXXXXX..... 13
b1d15                ...X....X..X...X..........X.....X.....XXXXXXX..... 13
id1                  .X...X...X.....................X....XX.X.....X.... 8
b1d14                ..X.....X.X...X...........X.....X.....XXXXXXX..... 13
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB12 ***********************************
Number of function block inputs used/remaining:               51/3
Number of signals used by logic mapping into function block:  51
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
ve4                   6       1<-   0   0     FB12_1        (b)     (b)
d28                   5       0     0   0     FB12_2  110   I/O     I/O
d27                   5       0     0   0     FB12_3  111   I/O     I/O
(unused)              0       0     0   5     FB12_4        (b)     
d26                   5       0     0   0     FB12_5  112   I/O     I/O
(unused)              0       0     0   5     FB12_6        (b)     
(unused)              0       0     0   5     FB12_7        (b)     
d25                   5       0     0   0     FB12_8  113   I/O     I/O
(unused)              0       0     0   5     FB12_9        (b)     
d24                   5       0     0   0     FB12_10 115   I/O     I/O
g0_OBUF/g0_OBUF_SETF__$INT
                      1       0     0   4     FB12_11       (b)     (b)
d23                   5       0     0   0     FB12_12 116   I/O     I/O
mski1                 4       0     0   1     FB12_13       (b)     (b)
mski0                 4       0   \/1   0     FB12_14       (b)     (b)
ve7                   6       1<-   0   0     FB12_15       (b)     (b)
(unused)              0       0   \/3   2     FB12_16       (b)     (b)
ve6                   6       3<- \/2   0     FB12_17       (b)     (b)
ve5                   6       2<- \/1   0     FB12_18       (b)     (b)

Signals Used by Logic in Function Block
  1: d16.PIN           18: b1d23                 35: inta 
  2: d17.PIN           19: b1d24                 36: intb 
  3: d4.PIN            20: b1d25                 37: intc 
  4: id7.PIN           21: b1d26                 38: intd 
  5: id8.PIN           22: b1d27                 39: lint 
  6: id9.PIN           23: b1d28                 40: mski0 
  7: id10.PIN          24: brst                  41: mski1 
  8: d5.PIN            25: d23                   42: prst 
  9: id11.PIN          26: d24                   43: rcs 
 10: id12.PIN          27: d25                   44: rst 
 11: tsiz0.PIN         28: d26                   45: rw 
 12: tsiz1.PIN         29: d27                   46: ta6 
 13: d6.PIN            30: d28                   47: ts6c 
 14: d7.PIN            31: d31_xcQ/d31_xcQ_TRST  48: ve4 
 15: a0                32: ide                   49: ve5 
 16: a1                33: idhlatch              50: ve6 
 17: a5                34: ieo                   51: ve7 

Signal                        1         2         3         4         5         6 FB
Name                0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs
ve4                  ..X.......XX..XXX................X........X.X.XX............ 11
d28                  .........X......X.....XX.....XXXXX...X....X.XXX............. 14
d27                  ........X.......X....X.X....X.XXXX..X.....X.XXX............. 14
d26                  ......X.........X...X..X...X..XXXX.X......X.XXX............. 14
d25                  .....X..........X..X...X..X...XXXXX.......X.XXX............. 14
d24                  ....X...........X.X....X.X....XXXX....X...X.XXX............. 14
g0_OBUF/g0_OBUF_SETF__$INT 
                     .........................................X.X................ 2
d23                  ...X............XX.....XX.....XXXX........X.XXX............. 13
mski1                .X........XX..XXX................X......X.X.X.X............. 11
mski0                X.........XX..XXX................X.....X..X.X.X............. 11
ve7                  ..........XX.XXXX................X........X.X.X...X......... 11
ve6                  ..........XXX.XXX................X........X.X.X..X.......... 11
ve5                  .......X..XX..XXX................X........X.X.X.X........... 11
                    0----+----1----+----2----+----3----+----4----+----5----+----6
                              0         0         0         0         0         0
*********************************** FB13 ***********************************
Number of function block inputs used/remaining:               43/11
Number of signals used by logic mapping into function block:  43
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b3d27                 3       0     0   2     FB13_1        (b)     (b)
id13                  4       0     0   1     FB13_2  71    I/O     I/O
b3d20                 3       0     0   2     FB13_3        (b)     (b)
b3d2                  3       0     0   2     FB13_4        (b)     (b)
b3d19                 3       0     0   2     FB13_5        (b)     (b)
b2d27                 3       0     0   2     FB13_6        (b)     (b)
b2d20                 3       0     0   2     FB13_7        (b)     (b)
id2                   4       0     0   1     FB13_8  74    I/O     I/O
b2d2                  3       0     0   2     FB13_9        (b)     (b)
b2d19                 3       0     0   2     FB13_10       (b)     (b)
id12                  4       0     0   1     FB13_11 75    I/O     I/O
b1d27                 3       0     0   2     FB13_12       (b)     (b)
b1d20                 3       0     0   2     FB13_13       (b)     (b)
id3                   4       0     0   1     FB13_14 76    I/O     I/O
id11                  4       0     0   1     FB13_15 77    I/O     I/O
b1d2                  3       0     0   2     FB13_16       (b)     (b)
id4                   4       0     0   1     FB13_17 78    I/O     I/O
b1d19                 3       0     0   2     FB13_18       (b)     (b)

Signals Used by Logic in Function Block
  1: d11.PIN           16: b1d2              30: b4d27 
  2: d12.PIN           17: b1d20             31: brst 
  3: d13.PIN           18: b1d27             32: ide 
  4: d2.PIN            19: b2d19             33: ieo 
  5: d20.PIN           20: b2d2              34: itr 
  6: d18.PIN           21: b2d20             35: long 
  7: d19.PIN           22: b2d27             36: peot 
  8: d3.PIN            23: b3d19             37: rw 
  9: d27.PIN           24: b3d2              38: shift 
 10: d28.PIN           25: b3d20             39: tacc0 
 11: d29.PIN           26: b3d27             40: tacc1 
 12: d4.PIN            27: b4d19             41: tacc2 
 13: ta6.PIN           28: b4d2              42: tacc3 
 14: a1                29: b4d20             43: ts6i 
 15: b1d19            

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b3d27                ........X...X............X...XX.X..XXXXXXX........ 13
id13                 ..X.......X..X.................X.XX.X.....X....... 8
b3d20                ....X.......X...........X...X.X.X..XXXXXXX........ 13
b3d2                 ...X........X..........X...X..X.X..XXXXXXX........ 13
b3d19                ......X.....X.........X...X...X.X..XXXXXXX........ 13
b2d27                ........X...X........X...X....X.X..XXXXXXX........ 13
b2d20                ....X.......X.......X...X.....X.X..XXXXXXX........ 13
id2                  ...X.X.......X.................X.XX.X.....X....... 8
b2d2                 ...X........X......X...X......X.X..XXXXXXX........ 13
b2d19                ......X.....X.....X...X.......X.X..XXXXXXX........ 13
id12                 .X.......X...X.................X.XX.X.....X....... 8
b1d27                ........X...X....X...X........X.X..XXXXXXX........ 13
b1d20                ....X.......X...X...X.........X.X..XXXXXXX........ 13
id3                  ......XX.....X.................X.XX.X.....X....... 8
id11                 X.......X....X.................X.XX.X.....X....... 8
b1d2                 ...X........X..X...X..........X.X..XXXXXXX........ 13
id4                  ....X......X.X.................X.XX.X.....X....... 8
b1d19                ......X.....X.X...X...........X.X..XXXXXXX........ 13
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB14 ***********************************
Number of function block inputs used/remaining:               44/10
Number of signals used by logic mapping into function block:  44
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
prst                  2       0     0   3     FB14_1        (b)     (b)
b4d31                 2       0     0   3     FB14_2        (b)     (b)
pcirst                1       0     0   4     FB14_3  100   I/O     O
b4d30                 2       0     0   3     FB14_4        (b)     (b)
b4d29                 2       0     0   3     FB14_5  101   I/O     I
b3d31                 3       0     0   2     FB14_6  102   I/O     I
b3d30                 3       0     0   2     FB14_7        (b)     (b)
b3d29                 3       0     0   2     FB14_8  103   I/O     I
b2d31                 3       0     0   2     FB14_9        (b)     (b)
b2d30                 3       0     0   2     FB14_10 104   I/O     I
d31                   5       0     0   0     FB14_11 105   I/O     I/O
b2d29                 3       0     0   2     FB14_12       (b)     (b)
b1d31                 3       0     0   2     FB14_13       (b)     (b)
d30                   5       0     0   0     FB14_14 106   I/O     I/O
d29                   5       0     0   0     FB14_15 107   I/O     I/O
b1d30                 3       0     0   2     FB14_16       (b)     (b)
b1d29                 3       0     0   2     FB14_17       (b)     (b)
b1d18                 3       0     0   2     FB14_18       (b)     (b)

Signals Used by Logic in Function Block
  1: d0.PIN            16: b2d29                 31: idhlatch 
  2: d18.PIN           17: b2d30                 32: ieo 
  3: d30.PIN           18: b2d31                 33: peot 
  4: d31.PIN           19: b3d29                 34: prst 
  5: d29.PIN           20: b3d30                 35: rcs 
  6: id13.PIN          21: b3d31                 36: rst 
  7: id14.PIN          22: b4d29                 37: rw 
  8: id15.PIN          23: b4d30                 38: shift 
  9: ta6.PIN           24: b4d31                 39: ta6 
 10: a5                25: brst                  40: tacc0 
 11: b1d18             26: d29                   41: tacc1 
 12: b1d29             27: d30                   42: tacc2 
 13: b1d30             28: d31                   43: tacc3 
 14: b1d31             29: d31_xcQ/d31_xcQ_TRST  44: ts6c 
 15: b2d18             30: ide                  

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
prst                 X........X.......................XX........X...... 5
b4d31                ...X....X..............XX......XX...X..XXXX....... 11
pcirst               .................................X.X.............. 2
b4d30                ..X.....X.............X.X......XX...X..XXXX....... 11
b4d29                ....X...X............X..X......XX...X..XXXX....... 11
b3d31                ...X....X...........X..XX......XX...XX.XXXX....... 13
b3d30                ..X.....X..........X..X.X......XX...XX.XXXX....... 13
b3d29                ....X...X.........X..X..X......XX...XX.XXXX....... 13
b2d31                ...X....X........X..X...X......XX...XX.XXXX....... 13
b2d30                ..X.....X.......X..X....X......XX...XX.XXXX....... 13
d31                  .......X.X...X..........X..XXXXX..X.X.X....X...... 13
b2d29                ....X...X......X..X.....X......XX...XX.XXXX....... 13
b1d31                ...X....X....X...X......X......XX...XX.XXXX....... 13
d30                  ......X..X..X...........X.X.XXXX..X.X.X....X...... 13
d29                  .....X...X.X............XX..XXXX..X.X.X....X...... 13
b1d30                ..X.....X...X...X.......X......XX...XX.XXXX....... 13
b1d29                ....X...X..X...X........X......XX...XX.XXXX....... 13
b1d18                .X......X.X...X.........X......XX...XX.XXXX....... 13
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB15 ***********************************
Number of function block inputs used/remaining:               47/7
Number of signals used by logic mapping into function block:  47
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b3d23                 3       0     0   2     FB15_1        (b)     (b)
id10                  4       0     0   1     FB15_2  79    I/O     I/O
id5                   4       0     0   1     FB15_3  80    I/O     I/O
b3d22                 3       0     0   2     FB15_4        (b)     (b)
b3d21                 3       0     0   2     FB15_5        (b)     (b)
b2d23                 3       0     0   2     FB15_6        (b)     (b)
b2d22                 3       0     0   2     FB15_7        (b)     (b)
id9                   4       0     0   1     FB15_8  81    I/O     I/O
b2d21                 3       0     0   2     FB15_9        (b)     (b)
id6                   4       0     0   1     FB15_10 82    I/O     I/O
id8                   4       0     0   1     FB15_11 83    I/O     I/O
id7                   4       0     0   1     FB15_12 85    I/O     I/O
b1d24                 3       0     0   2     FB15_13       (b)     (b)
ccs                   1       0     0   4     FB15_14 86    I/O     O
g0                    1       0     0   4     FB15_15 87    I/O     O
b1d23                 3       0     0   2     FB15_16       (b)     (b)
b1d22                 3       0     0   2     FB15_17 88    I/O     I
b1d21                 3       0     0   2     FB15_18       (b)     (b)

Signals Used by Logic in Function Block
  1: d10.PIN           17: a29               33: b4d23 
  2: d21.PIN           18: a30               34: brst 
  3: d22.PIN           19: a31               35: g0_OBUF/g0_OBUF_SETF__$INT 
  4: d23.PIN           20: b1d21             36: ide 
  5: d24.PIN           21: b1d22             37: ieo 
  6: d25.PIN           22: b1d23             38: itr 
  7: d26.PIN           23: b1d24             39: long 
  8: d5.PIN            24: b2d21             40: peot 
  9: ta6.PIN           25: b2d22             41: rw 
 10: d6.PIN            26: b2d23             42: shift 
 11: d7.PIN            27: b2d24             43: tacc0 
 12: d8.PIN            28: b3d21             44: tacc1 
 13: d9.PIN            29: b3d22             45: tacc2 
 14: a1                30: b3d23             46: tacc3 
 15: a27               31: b4d21             47: ts6i 
 16: a28               32: b4d22            

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b3d23                ...X....X....................X..XX..X..XXXXXXX.... 13
id10                 X.....X......X.....................X.XX.X.....X... 8
id5                  .X.....X.....X.....................X.XX.X.....X... 8
b3d22                ..X.....X...................X..X.X..X..XXXXXXX.... 13
b3d21                .X......X..................X..X..X..X..XXXXXXX.... 13
b2d23                ...X....X................X...X...X..X..XXXXXXX.... 13
b2d22                ..X.....X...............X...X....X..X..XXXXXXX.... 13
id9                  .....X......XX.....................X.XX.X.....X... 8
b2d21                .X......X..............X...X.....X..X..XXXXXXX.... 13
id6                  ..X......X...X.....................X.XX.X.....X... 8
id8                  ....X......X.X.....................X.XX.X.....X... 8
id7                  ...X......X..X.....................X.XX.X.....X... 8
b1d24                ....X...X.............X...X......X..X..XXXXXXX.... 13
ccs                  ..............XXXXX............................... 5
g0                   ..................................X............... 1
b1d23                ...X....X............X...X.......X..X..XXXXXXX.... 13
b1d22                ..X.....X...........X...X........X..X..XXXXXXX.... 13
b1d21                .X......X..........X...X.........X..X..XXXXXXX.... 13
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*********************************** FB16 ***********************************
Number of function block inputs used/remaining:               40/14
Number of signals used by logic mapping into function block:  40
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
b4d7                  2       0     0   3     FB16_1        (b)     (b)
b4d4                  2       0     0   3     FB16_2  91    I/O     I
b4d3                  2       0     0   3     FB16_3  92    I/O     I
b3d7                  3       0   \/2   0     FB16_4        (b)     (b)
g4                    7       2<-   0   0     FB16_5  93    I/O     O
g3                    7       2<-   0   0     FB16_6  94    I/O     O
b3d4                  3       0   /\2   0     FB16_7        (b)     (b)
g2                    7       2<-   0   0     FB16_8  95    I/O     O
b3d3                  3       0   /\2   0     FB16_9        (b)     (b)
b2d8                  3       0     0   2     FB16_10 96    I/O     I
g1                    7       2<-   0   0     FB16_11 97    I/O     O
b2d7                  3       0   /\2   0     FB16_12 98    I/O     I
b2d4                  3       0     0   2     FB16_13       (b)     (b)
b2d3                  3       0     0   2     FB16_14       (b)     (b)
b1d8                  3       0     0   2     FB16_15       (b)     (b)
b1d7                  3       0     0   2     FB16_16       (b)     (b)
b1d4                  3       0     0   2     FB16_17       (b)     (b)
b1d3                  3       0     0   2     FB16_18       (b)     (b)

Signals Used by Logic in Function Block
  1: d3.PIN            15: b3d4                        28: ieo 
  2: d4.PIN            16: b3d7                        29: peot 
  3: ta6.PIN           17: b3d8                        30: r0 
  4: d7.PIN            18: b4d3                        31: r1 
  5: d8.PIN            19: b4d4                        32: r2 
  6: b1d3              20: b4d7                        33: r3 
  7: b1d4              21: brst                        34: r4 
  8: b1d7              22: g0                          35: rw 
  9: b1d8              23: g0_OBUF/g0_OBUF_SETF__$INT  36: shift 
 10: b2d3              24: g1                          37: tacc0 
 11: b2d4              25: g2                          38: tacc1 
 12: b2d7              26: g3                          39: tacc2 
 13: b2d8              27: g4                          40: tacc3 
 14: b3d3             

Signal                        1         2         3         4         5 FB
Name                0----+----0----+----0----+----0----+----0----+----0 Inputs
b4d7                 ..XX...............XX......XX.....X.XXXX.......... 11
b4d4                 .XX...............X.X......XX.....X.XXXX.......... 11
b4d3                 X.X..............X..X......XX.....X.XXXX.......... 11
b3d7                 ..XX...........X...XX......XX.....XXXXXX.......... 13
g4                   .....................XXXXXX..XXXXX................ 11
g3                   .....................XXXXXX..XXXXX................ 11
b3d4                 .XX...........X...X.X......XX.....XXXXXX.......... 13
g2                   .....................XXXXXX..XXXXX................ 11
b3d3                 X.X..........X...X..X......XX.....XXXXXX.......... 13
b2d8                 ..X.X.......X...X...X......XX.....XXXXXX.......... 13
g1                   .....................XXXXXX..XXXXX................ 11
b2d7                 ..XX.......X...X....X......XX.....XXXXXX.......... 13
b2d4                 .XX.......X...X.....X......XX.....XXXXXX.......... 13
b2d3                 X.X......X...X......X......XX.....XXXXXX.......... 13
b1d8                 ..X.X...X...X.......X......XX.....XXXXXX.......... 13
b1d7                 ..XX...X...X........X......XX.....XXXXXX.......... 13
b1d4                 .XX...X...X.........X......XX.....XXXXXX.......... 13
b1d3                 X.X..X...X..........X......XX.....XXXXXX.......... 13
                    0----+----1----+----2----+----3----+----4----+----5
                              0         0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********

b1d0.D = b1d0 & !shift & !peot
	# rw & b2d0 & shift & !peot & ieo
	# rw & !ta6.PIN & d0.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d0.CLK = ctclk;	// GCK    

b1d1.D = b1d1 & !shift & !peot
	# rw & b2d1 & shift & !peot & ieo
	# rw & !ta6.PIN & d1.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d1.CLK = ctclk;	// GCK    

b1d10.D = b1d10 & !shift & !peot
	# rw & b2d10 & shift & !peot & ieo
	# rw & !ta6.PIN & d10.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d10.CLK = ctclk;	// GCK    

b1d11.D = b1d11 & !shift & !peot
	# rw & b2d11 & shift & !peot & ieo
	# rw & !ta6.PIN & d11.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d11.CLK = ctclk;	// GCK    

b1d12.D = b1d12 & !shift & !peot
	# rw & b2d12 & shift & !peot & ieo
	# rw & !ta6.PIN & d12.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d12.CLK = ctclk;	// GCK    

b1d13.D = b1d13 & !shift & !peot
	# rw & b2d13 & shift & !peot & ieo
	# rw & !ta6.PIN & d13.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d13.CLK = ctclk;	// GCK    

b1d14.D = b1d14 & !shift & !peot
	# rw & b2d14 & shift & !peot & ieo
	# rw & !ta6.PIN & d14.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d14.CLK = ctclk;	// GCK    

b1d15.D = b1d15 & !shift & !peot
	# rw & b2d15 & shift & !peot & ieo
	# rw & !ta6.PIN & d15.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d15.CLK = ctclk;	// GCK    

b1d16.D = b1d16 & !shift & !peot
	# rw & b2d16 & shift & !peot & ieo
	# rw & !ta6.PIN & d16.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d16.CLK = ctclk;	// GCK    

b1d17.D = b1d17 & !shift & !peot
	# rw & b2d17 & shift & !peot & ieo
	# rw & !ta6.PIN & d17.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d17.CLK = ctclk;	// GCK    

b1d18.D = b1d18 & !shift & !peot
	# rw & b2d18 & shift & !peot & ieo
	# rw & !ta6.PIN & d18.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d18.CLK = ctclk;	// GCK    

b1d19.D = b1d19 & !shift & !peot
	# rw & b2d19 & shift & !peot & ieo
	# rw & !ta6.PIN & d19.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d19.CLK = ctclk;	// GCK    

b1d2.D = b1d2 & !shift & !peot
	# rw & b2d2 & shift & !peot & ieo
	# rw & !ta6.PIN & d2.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d2.CLK = ctclk;	// GCK    

b1d20.D = b1d20 & !shift & !peot
	# rw & b2d20 & shift & !peot & ieo
	# rw & !ta6.PIN & d20.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d20.CLK = ctclk;	// GCK    

b1d21.D = b1d21 & !shift & !peot
	# rw & b2d21 & shift & !peot & ieo
	# rw & !ta6.PIN & d21.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d21.CLK = ctclk;	// GCK    

b1d22.D = b1d22 & !shift & !peot
	# rw & b2d22 & shift & !peot & ieo
	# rw & !ta6.PIN & d22.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d22.CLK = ctclk;	// GCK    

b1d23.D = b1d23 & !shift & !peot
	# rw & b2d23 & shift & !peot & ieo
	# rw & !ta6.PIN & d23.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d23.CLK = ctclk;	// GCK    

b1d24.D = b1d24 & !shift & !peot
	# rw & b2d24 & shift & !peot & ieo
	# rw & !ta6.PIN & d24.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d24.CLK = ctclk;	// GCK    

b1d25.D = b1d25 & !shift & !peot
	# rw & b2d25 & shift & !peot & ieo
	# rw & !ta6.PIN & d25.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d25.CLK = ctclk;	// GCK    

b1d26.D = b1d26 & !shift & !peot
	# rw & b2d26 & shift & !peot & ieo
	# rw & !ta6.PIN & d26.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d26.CLK = ctclk;	// GCK    

b1d27.D = b1d27 & !shift & !peot
	# rw & b2d27 & shift & !peot & ieo
	# rw & !ta6.PIN & d27.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d27.CLK = ctclk;	// GCK    

b1d28.D = b1d28 & !shift & !peot
	# rw & b2d28 & shift & !peot & ieo
	# rw & !ta6.PIN & d28.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d28.CLK = ctclk;	// GCK    

b1d29.D = b1d29 & !shift & !peot
	# rw & b2d29 & shift & !peot & ieo
	# rw & !ta6.PIN & d29.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d29.CLK = ctclk;	// GCK    

b1d3.D = b1d3 & !shift & !peot
	# rw & b2d3 & shift & !peot & ieo
	# rw & !ta6.PIN & d3.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d3.CLK = ctclk;	// GCK    

b1d30.D = b1d30 & !shift & !peot
	# rw & b2d30 & shift & !peot & ieo
	# rw & !ta6.PIN & d30.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d30.CLK = ctclk;	// GCK    

b1d31.D = b1d31 & !shift & !peot
	# rw & b2d31 & shift & !peot & ieo
	# rw & !ta6.PIN & d31.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d31.CLK = ctclk;	// GCK    

b1d4.D = b1d4 & !shift & !peot
	# rw & b2d4 & shift & !peot & ieo
	# rw & !ta6.PIN & d4.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d4.CLK = ctclk;	// GCK    

b1d5.D = b1d5 & !shift & !peot
	# rw & b2d5 & shift & !peot & ieo
	# rw & !ta6.PIN & d5.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d5.CLK = ctclk;	// GCK    

b1d6.D = b1d6 & !shift & !peot
	# rw & b2d6 & shift & !peot & ieo
	# rw & !ta6.PIN & d6.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d6.CLK = ctclk;	// GCK    

b1d7.D = b1d7 & !shift & !peot
	# rw & b2d7 & shift & !peot & ieo
	# rw & !ta6.PIN & d7.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d7.CLK = ctclk;	// GCK    

b1d8.D = b1d8 & !shift & !peot
	# rw & b2d8 & shift & !peot & ieo
	# rw & !ta6.PIN & d8.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d8.CLK = ctclk;	// GCK    

b1d9.D = b1d9 & !shift & !peot
	# rw & b2d9 & shift & !peot & ieo
	# rw & !ta6.PIN & d9.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & !tacc0;
   b1d9.CLK = ctclk;	// GCK    

b2d0.D = b2d0 & !shift & !peot
	# rw & b3d0 & shift & !peot & ieo
	# rw & !ta6.PIN & d0.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d0.CLK = ctclk;	// GCK    

b2d1.D = b2d1 & !shift & !peot
	# rw & b3d1 & shift & !peot & ieo
	# rw & !ta6.PIN & d1.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d1.CLK = ctclk;	// GCK    

b2d10.D = b2d10 & !shift & !peot
	# rw & b3d10 & shift & !peot & ieo
	# rw & !ta6.PIN & d10.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d10.CLK = ctclk;	// GCK    

b2d11.D = b2d11 & !shift & !peot
	# rw & b3d11 & shift & !peot & ieo
	# rw & !ta6.PIN & d11.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d11.CLK = ctclk;	// GCK    

b2d12.D = b2d12 & !shift & !peot
	# rw & b3d12 & shift & !peot & ieo
	# rw & !ta6.PIN & d12.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d12.CLK = ctclk;	// GCK    

b2d13.D = b2d13 & !shift & !peot
	# rw & b3d13 & shift & !peot & ieo
	# rw & !ta6.PIN & d13.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d13.CLK = ctclk;	// GCK    

b2d14.D = b2d14 & !shift & !peot
	# rw & b3d14 & shift & !peot & ieo
	# rw & !ta6.PIN & d14.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d14.CLK = ctclk;	// GCK    

b2d15.D = b2d15 & !shift & !peot
	# rw & b3d15 & shift & !peot & ieo
	# rw & !ta6.PIN & d15.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d15.CLK = ctclk;	// GCK    

b2d16.D = b2d16 & !shift & !peot
	# rw & b3d16 & shift & !peot & ieo
	# rw & !ta6.PIN & d16.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d16.CLK = ctclk;	// GCK    

b2d17.D = b2d17 & !shift & !peot
	# rw & b3d17 & shift & !peot & ieo
	# rw & !ta6.PIN & d17.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d17.CLK = ctclk;	// GCK    

b2d18.D = b2d18 & !shift & !peot
	# rw & b3d18 & shift & !peot & ieo
	# rw & !ta6.PIN & d18.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d18.CLK = ctclk;	// GCK    

b2d19.D = b2d19 & !shift & !peot
	# rw & b3d19 & shift & !peot & ieo
	# rw & !ta6.PIN & d19.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d19.CLK = ctclk;	// GCK    

b2d2.D = b2d2 & !shift & !peot
	# rw & b3d2 & shift & !peot & ieo
	# rw & !ta6.PIN & d2.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d2.CLK = ctclk;	// GCK    

b2d20.D = b2d20 & !shift & !peot
	# rw & b3d20 & shift & !peot & ieo
	# rw & !ta6.PIN & d20.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d20.CLK = ctclk;	// GCK    

b2d21.D = b2d21 & !shift & !peot
	# rw & b3d21 & shift & !peot & ieo
	# rw & !ta6.PIN & d21.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d21.CLK = ctclk;	// GCK    

b2d22.D = b2d22 & !shift & !peot
	# rw & b3d22 & shift & !peot & ieo
	# rw & !ta6.PIN & d22.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d22.CLK = ctclk;	// GCK    

b2d23.D = b2d23 & !shift & !peot
	# rw & b3d23 & shift & !peot & ieo
	# rw & !ta6.PIN & d23.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d23.CLK = ctclk;	// GCK    

b2d24.D = b2d24 & !shift & !peot
	# rw & b3d24 & shift & !peot & ieo
	# rw & !ta6.PIN & d24.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d24.CLK = ctclk;	// GCK    

b2d25.D = b2d25 & !shift & !peot
	# rw & b3d25 & shift & !peot & ieo
	# rw & !ta6.PIN & d25.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d25.CLK = ctclk;	// GCK    

b2d26.D = b2d26 & !shift & !peot
	# rw & b3d26 & shift & !peot & ieo
	# rw & !ta6.PIN & d26.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d26.CLK = ctclk;	// GCK    

b2d27.D = b2d27 & !shift & !peot
	# rw & b3d27 & shift & !peot & ieo
	# rw & !ta6.PIN & d27.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d27.CLK = ctclk;	// GCK    

b2d28.D = b2d28 & !shift & !peot
	# rw & b3d28 & shift & !peot & ieo
	# rw & !ta6.PIN & d28.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d28.CLK = ctclk;	// GCK    

b2d29.D = b2d29 & !shift & !peot
	# rw & b3d29 & shift & !peot & ieo
	# rw & !ta6.PIN & d29.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d29.CLK = ctclk;	// GCK    

b2d3.D = b2d3 & !shift & !peot
	# rw & b3d3 & shift & !peot & ieo
	# rw & !ta6.PIN & d3.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d3.CLK = ctclk;	// GCK    

b2d30.D = b2d30 & !shift & !peot
	# rw & b3d30 & shift & !peot & ieo
	# rw & !ta6.PIN & d30.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d30.CLK = ctclk;	// GCK    

b2d31.D = b2d31 & !shift & !peot
	# rw & b3d31 & shift & !peot & ieo
	# rw & !ta6.PIN & d31.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d31.CLK = ctclk;	// GCK    

b2d4.D = b2d4 & !shift & !peot
	# rw & b3d4 & shift & !peot & ieo
	# rw & !ta6.PIN & d4.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d4.CLK = ctclk;	// GCK    

b2d5.D = b2d5 & !shift & !peot
	# rw & b3d5 & shift & !peot & ieo
	# rw & !ta6.PIN & d5.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d5.CLK = ctclk;	// GCK    

b2d6.D = b2d6 & !shift & !peot
	# rw & b3d6 & shift & !peot & ieo
	# rw & !ta6.PIN & d6.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d6.CLK = ctclk;	// GCK    

b2d7.D = b2d7 & !shift & !peot
	# rw & b3d7 & shift & !peot & ieo
	# rw & !ta6.PIN & d7.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d7.CLK = ctclk;	// GCK    

b2d8.D = b2d8 & !shift & !peot
	# rw & b3d8 & shift & !peot & ieo
	# rw & !ta6.PIN & d8.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d8.CLK = ctclk;	// GCK    

b2d9.D = b2d9 & !shift & !peot
	# rw & b3d9 & shift & !peot & ieo
	# rw & !ta6.PIN & d9.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & !tacc1 & brst & tacc0;
   b2d9.CLK = ctclk;	// GCK    

b3d0.D = b3d0 & !shift & !peot
	# rw & b4d0 & shift & !peot & ieo
	# rw & !ta6.PIN & d0.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d0.CLK = ctclk;	// GCK    

b3d1.D = b3d1 & !shift & !peot
	# rw & b4d1 & shift & !peot & ieo
	# rw & !ta6.PIN & d1.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d1.CLK = ctclk;	// GCK    

b3d10.D = b3d10 & !shift & !peot
	# rw & b4d10 & shift & !peot & ieo
	# rw & !ta6.PIN & d10.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d10.CLK = ctclk;	// GCK    

b3d11.D = b3d11 & !shift & !peot
	# rw & b4d11 & shift & !peot & ieo
	# rw & !ta6.PIN & d11.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d11.CLK = ctclk;	// GCK    

b3d12.D = b3d12 & !shift & !peot
	# rw & b4d12 & shift & !peot & ieo
	# rw & !ta6.PIN & d12.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d12.CLK = ctclk;	// GCK    

b3d13.D = b3d13 & !shift & !peot
	# rw & b4d13 & shift & !peot & ieo
	# rw & !ta6.PIN & d13.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d13.CLK = ctclk;	// GCK    

b3d14.D = b3d14 & !shift & !peot
	# rw & b4d14 & shift & !peot & ieo
	# rw & !ta6.PIN & d14.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d14.CLK = ctclk;	// GCK    

b3d15.D = b3d15 & !shift & !peot
	# rw & b4d15 & shift & !peot & ieo
	# rw & !ta6.PIN & d15.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d15.CLK = ctclk;	// GCK    

b3d16.D = b3d16 & !shift & !peot
	# rw & b4d16 & shift & !peot & ieo
	# rw & !ta6.PIN & d16.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d16.CLK = ctclk;	// GCK    

b3d17.D = b3d17 & !shift & !peot
	# rw & b4d17 & shift & !peot & ieo
	# rw & !ta6.PIN & d17.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d17.CLK = ctclk;	// GCK    

b3d18.D = b3d18 & !shift & !peot
	# rw & b4d18 & shift & !peot & ieo
	# rw & !ta6.PIN & d18.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d18.CLK = ctclk;	// GCK    

b3d19.D = b3d19 & !shift & !peot
	# rw & b4d19 & shift & !peot & ieo
	# rw & !ta6.PIN & d19.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d19.CLK = ctclk;	// GCK    

b3d2.D = b3d2 & !shift & !peot
	# rw & b4d2 & shift & !peot & ieo
	# rw & !ta6.PIN & d2.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d2.CLK = ctclk;	// GCK    

b3d20.D = b3d20 & !shift & !peot
	# rw & b4d20 & shift & !peot & ieo
	# rw & !ta6.PIN & d20.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d20.CLK = ctclk;	// GCK    

b3d21.D = b3d21 & !shift & !peot
	# rw & b4d21 & shift & !peot & ieo
	# rw & !ta6.PIN & d21.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d21.CLK = ctclk;	// GCK    

b3d22.D = b3d22 & !shift & !peot
	# rw & b4d22 & shift & !peot & ieo
	# rw & !ta6.PIN & d22.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d22.CLK = ctclk;	// GCK    

b3d23.D = b3d23 & !shift & !peot
	# rw & b4d23 & shift & !peot & ieo
	# rw & !ta6.PIN & d23.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d23.CLK = ctclk;	// GCK    

b3d24.D = b3d24 & !shift & !peot
	# rw & b4d24 & shift & !peot & ieo
	# rw & !ta6.PIN & d24.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d24.CLK = ctclk;	// GCK    

b3d25.D = b3d25 & !shift & !peot
	# rw & b4d25 & shift & !peot & ieo
	# rw & !ta6.PIN & d25.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d25.CLK = ctclk;	// GCK    

b3d26.D = b3d26 & !shift & !peot
	# rw & b4d26 & shift & !peot & ieo
	# rw & !ta6.PIN & d26.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d26.CLK = ctclk;	// GCK    

b3d27.D = b3d27 & !shift & !peot
	# rw & b4d27 & shift & !peot & ieo
	# rw & !ta6.PIN & d27.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d27.CLK = ctclk;	// GCK    

b3d28.D = b3d28 & !shift & !peot
	# rw & b4d28 & shift & !peot & ieo
	# rw & !ta6.PIN & d28.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d28.CLK = ctclk;	// GCK    

b3d29.D = b3d29 & !shift & !peot
	# rw & b4d29 & shift & !peot & ieo
	# rw & !ta6.PIN & d29.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d29.CLK = ctclk;	// GCK    

b3d3.D = b3d3 & !shift & !peot
	# rw & b4d3 & shift & !peot & ieo
	# rw & !ta6.PIN & d3.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d3.CLK = ctclk;	// GCK    

b3d30.D = b3d30 & !shift & !peot
	# rw & b4d30 & shift & !peot & ieo
	# rw & !ta6.PIN & d30.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d30.CLK = ctclk;	// GCK    

b3d31.D = b3d31 & !shift & !peot
	# rw & b4d31 & shift & !peot & ieo
	# rw & !ta6.PIN & d31.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d31.CLK = ctclk;	// GCK    

b3d4.D = b3d4 & !shift & !peot
	# rw & b4d4 & shift & !peot & ieo
	# rw & !ta6.PIN & d4.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d4.CLK = ctclk;	// GCK    

b3d5.D = b3d5 & !shift & !peot
	# rw & b4d5 & shift & !peot & ieo
	# rw & !ta6.PIN & d5.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d5.CLK = ctclk;	// GCK    

b3d6.D = b3d6 & !shift & !peot
;Imported pterms FB6_12
	# rw & b4d6 & shift & !peot & ieo
	# rw & !ta6.PIN & d6.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d6.CLK = ctclk;	// GCK    

b3d7.D = b3d7 & !shift & !peot
	# rw & b4d7 & shift & !peot & ieo
	# rw & !ta6.PIN & d7.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d7.CLK = ctclk;	// GCK    

b3d8.D = b3d8 & !shift & !peot
	# rw & b4d8 & shift & !peot & ieo
	# rw & !ta6.PIN & d8.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d8.CLK = ctclk;	// GCK    

b3d9.D = b3d9 & !shift & !peot
	# rw & b4d9 & shift & !peot & ieo
	# rw & !ta6.PIN & d9.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & !tacc0;
   b3d9.CLK = ctclk;	// GCK    

b4d0.D = b4d0 & !peot
	# rw & !ta6.PIN & d0.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d0.CLK = ctclk;	// GCK    

b4d1.D = b4d1 & !peot
	# rw & !ta6.PIN & d1.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d1.CLK = ctclk;	// GCK    

b4d10.D = b4d10 & !peot
	# rw & !ta6.PIN & d10.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d10.CLK = ctclk;	// GCK    

b4d11.D = b4d11 & !peot
	# rw & !ta6.PIN & d11.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d11.CLK = ctclk;	// GCK    

b4d12.D = b4d12 & !peot
	# rw & !ta6.PIN & d12.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d12.CLK = ctclk;	// GCK    

b4d13.D = b4d13 & !peot
	# rw & !ta6.PIN & d13.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d13.CLK = ctclk;	// GCK    

b4d14.D = b4d14 & !peot
	# rw & !ta6.PIN & d14.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d14.CLK = ctclk;	// GCK    

b4d15.D = b4d15 & !peot
	# rw & !ta6.PIN & d15.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d15.CLK = ctclk;	// GCK    

b4d16.D = b4d16 & !peot
	# rw & !ta6.PIN & d16.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d16.CLK = ctclk;	// GCK    

b4d17.D = b4d17 & !peot
	# rw & !ta6.PIN & d17.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d17.CLK = ctclk;	// GCK    

b4d18.D = b4d18 & !peot
	# rw & !ta6.PIN & d18.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d18.CLK = ctclk;	// GCK    

b4d19.D = b4d19 & !peot
	# rw & !ta6.PIN & d19.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d19.CLK = ctclk;	// GCK    

b4d2.D = b4d2 & !peot
	# rw & !ta6.PIN & d2.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d2.CLK = ctclk;	// GCK    

b4d20.D = b4d20 & !peot
	# rw & !ta6.PIN & d20.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d20.CLK = ctclk;	// GCK    

b4d21.D = b4d21 & !peot
	# rw & !ta6.PIN & d21.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d21.CLK = ctclk;	// GCK    

b4d22.D = b4d22 & !peot
	# rw & !ta6.PIN & d22.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d22.CLK = ctclk;	// GCK    

b4d23.D = b4d23 & !peot
	# rw & !ta6.PIN & d23.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d23.CLK = ctclk;	// GCK    

b4d24.D = b4d24 & !peot
	# rw & !ta6.PIN & d24.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d24.CLK = ctclk;	// GCK    

b4d25.D = b4d25 & !peot
	# rw & !ta6.PIN & d25.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d25.CLK = ctclk;	// GCK    

b4d26.D = b4d26 & !peot
	# rw & !ta6.PIN & d26.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d26.CLK = ctclk;	// GCK    

b4d27.D = b4d27 & !peot
	# rw & !ta6.PIN & d27.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d27.CLK = ctclk;	// GCK    

b4d28.D = b4d28 & !peot
	# rw & !ta6.PIN & d28.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d28.CLK = ctclk;	// GCK    

b4d29.D = b4d29 & !peot
	# rw & !ta6.PIN & d29.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d29.CLK = ctclk;	// GCK    

b4d3.D = b4d3 & !peot
	# rw & !ta6.PIN & d3.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d3.CLK = ctclk;	// GCK    

b4d30.D = b4d30 & !peot
	# rw & !ta6.PIN & d30.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d30.CLK = ctclk;	// GCK    

b4d31.D = b4d31 & !peot
	# rw & !ta6.PIN & d31.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d31.CLK = ctclk;	// GCK    

b4d4.D = b4d4 & !peot
	# rw & !ta6.PIN & d4.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d4.CLK = ctclk;	// GCK    

b4d5.D = b4d5 & !peot
	# rw & !ta6.PIN & d5.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d5.CLK = ctclk;	// GCK    

b4d6.D = b4d6 & !peot
	# rw & !ta6.PIN & d6.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d6.CLK = ctclk;	// GCK    

b4d7.D = b4d7 & !peot
	# rw & !ta6.PIN & d7.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d7.CLK = ctclk;	// GCK    

b4d8.D = b4d8 & !peot
	# rw & !ta6.PIN & d8.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d8.CLK = ctclk;	// GCK    

b4d9.D = b4d9 & !peot
	# rw & !ta6.PIN & d9.PIN & !tacc3 & !tacc2 & !peot & 
	ieo & tacc1 & brst & tacc0;
   b4d9.CLK = ctclk;	// GCK    

bdip.D = bdip & tsp
	# bdip & !pci
	# bdip & !brst6
	# !tap.PIN & !tapcc0 & tapcc1;
   bdip.CLK = pxclk;	// GCK
   !bdip.AP = rst;	// GSR
   bdip.OE = !ieo;    

!bgplx.D = !bg60 & !brplx;
   bgplx.CLK = ctclk;	// GCK    

!bgslt.D = !bg60 & brplx & !brslt & bgplx;
   bgslt.CLK = ctclk;	// GCK    

bi = !ieo;    

br60.D = brplx & brslt;
   br60.CLK = ctclk;	// GCK    

brst = rw & !ieo & siz1.PIN & siz0.PIN & pci;    

brst6 = siz1.PIN & siz0.PIN;    

!bs0 = !tsiz1.PIN & !a1 & !a0 & ieo
	# !a1 & !a0 & !tsiz0.PIN & ieo;
   bs0.OE = !bb & ieo;    

!bs1 = !tsiz1.PIN & !a1 & !a0 & ieo
	# tsiz1.PIN & !a1 & a0 & !tsiz0.PIN & ieo;
   bs1.OE = !bb & ieo;    

!bs2 = tsiz1.PIN & a1 & !a0 & !tsiz0.PIN & ieo
	# !tsiz1.PIN & a1 & !a0 & tsiz0.PIN & ieo
	# !tsiz1.PIN & !a1 & !a0 & !tsiz0.PIN & ieo;
   bs2.OE = !bb & ieo;    

!bs3 = tsiz1.PIN & a1 & a0 & !tsiz0.PIN & ieo
	# !tsiz1.PIN & a1 & !a0 & tsiz0.PIN & ieo
	# !tsiz1.PIN & !a1 & !a0 & !tsiz0.PIN & ieo;
   bs3.OE = !bb & ieo;    

!burst = siz1.PIN & siz0.PIN & pci;
   burst.OE = !ieo;    

!ccs = a30 & a31 & a29 & a27 & !a28;    

!cs0 = !a5 & ts6i;    

!cs1 = a5 & ts6i;    

d0.D = id0.PIN & idllatch
	# !ide & d0 & ta6
	# !lint & mski0 & iack6 & vect0
	# rw & b1d0 & ieo & brst
;Imported pterms FB4_3
	# !intd & mski4 & iack6 & vect0
	# !intc & mski3 & iack6 & vect0
	# !intb & mski2 & iack6 & vect0
	# !inta & mski1 & iack6 & vect0;
   d0.CLK = ctclk;	// GCK
   d0.OE = d7_xcQ/d7_xcQ_TRST;    

d1.D = id1.PIN & idllatch
	# !ide & d1 & ta6
	# !lint & mski0 & iack6 & vect1
	# rw & b1d1 & ieo & brst
;Imported pterms FB4_4
	# !intd & mski4 & iack6 & vect1
	# !intc & mski3 & iack6 & vect1
	# !intb & mski2 & iack6 & vect1
	# !inta & mski1 & iack6 & vect1;
   d1.CLK = ctclk;	// GCK
   d1.OE = d7_xcQ/d7_xcQ_TRST;    

d10.D = id10.PIN & idllatch
	# !ide & d10 & ta6
	# rw & b1d10 & ieo & brst;
   d10.CLK = ctclk;	// GCK
   d10.OE = d9_xcQ/d9_xcQ_TRST;    

d11.D = id11.PIN & idllatch
	# !ide & d11 & ta6
	# rw & b1d11 & ieo & brst;
   d11.CLK = ctclk;	// GCK
   d11.OE = d9_xcQ/d9_xcQ_TRST;    

d12.D = id12.PIN & idllatch
	# !ide & d12 & ta6
	# rw & b1d12 & ieo & brst;
   d12.CLK = ctclk;	// GCK
   d12.OE = d9_xcQ/d9_xcQ_TRST;    

d13.D = id13.PIN & idllatch
	# !ide & d13 & ta6
	# rw & b1d13 & ieo & brst;
   d13.CLK = ctclk;	// GCK
   d13.OE = d9_xcQ/d9_xcQ_TRST;    

d14.D = id14.PIN & idllatch
	# !ide & d14 & ta6
	# rw & b1d14 & ieo & brst;
   d14.CLK = ctclk;	// GCK
   d14.OE = d9_xcQ/d9_xcQ_TRST;    

d15.D = id15.PIN & idllatch
	# !ide & d15 & ta6
	# rw & b1d15 & ieo & brst;
   d15.CLK = ctclk;	// GCK
   d15.OE = d9_xcQ/d9_xcQ_TRST;    

d16.D = id0.PIN & idhlatch
	# !ide & d16 & ta6
	# rw & b1d16 & ieo & brst
	# rw & !a5 & mski0 & ts6c & rcs;
   d16.CLK = ctclk;	// GCK
   d16.OE = d31_xcQ/d31_xcQ_TRST;    

d17.D = id1.PIN & idhlatch
	# !ide & d17 & ta6
	# rw & b1d17 & ieo & brst
	# rw & !a5 & mski1 & ts6c & rcs;
   d17.CLK = ctclk;	// GCK
   d17.OE = d31_xcQ/d31_xcQ_TRST;    

d18.D = id2.PIN & idhlatch
	# !ide & d18 & ta6
	# rw & b1d18 & ieo & brst
	# rw & !a5 & mski2 & ts6c & rcs;
   d18.CLK = ctclk;	// GCK
   d18.OE = d31_xcQ/d31_xcQ_TRST;    

d19.D = id3.PIN & idhlatch
	# !ide & d19 & ta6
	# rw & b1d19 & ieo & brst
	# rw & !a5 & mski3 & ts6c & rcs;
   d19.CLK = ctclk;	// GCK
   d19.OE = d31_xcQ/d31_xcQ_TRST;    

d2.D = id2.PIN & idllatch
	# !ide & d2 & ta6
	# !lint & mski0 & iack6 & vect2
	# rw & b1d2 & ieo & brst
;Imported pterms FB4_7
	# !intd & mski4 & iack6 & vect2
	# !intc & mski3 & iack6 & vect2
	# !intb & mski2 & iack6 & vect2
	# !inta & mski1 & iack6 & vect2;
   d2.CLK = ctclk;	// GCK
   d2.OE = d7_xcQ/d7_xcQ_TRST;    

d20.D = id4.PIN & idhlatch
	# !ide & d20 & ta6
	# rw & b1d20 & ieo & brst
	# rw & !a5 & mski4 & ts6c & rcs;
   d20.CLK = ctclk;	// GCK
   d20.OE = d31_xcQ/d31_xcQ_TRST;    

d21.D = id5.PIN & idhlatch
	# !ide & d21 & ta6
	# rw & !a5 & ts6c & rcs
	# rw & b1d21 & ieo & brst;
   d21.CLK = ctclk;	// GCK
   d21.OE = d31_xcQ/d31_xcQ_TRST;    

d22.D = id6.PIN & idhlatch
	# !ide & d22 & ta6
	# rw & !a5 & ts6c & rcs
	# rw & b1d22 & ieo & brst;
   d22.CLK = ctclk;	// GCK
   d22.OE = d31_xcQ/d31_xcQ_TRST;    

d23.D = id7.PIN & idhlatch
	# !ide & d23 & ta6
	# rw & !a5 & ts6c & rcs
	# rw & b1d23 & ieo & brst;
   d23.CLK = ctclk;	// GCK
   d23.OE = d31_xcQ/d31_xcQ_TRST;    

d24.D = id8.PIN & idhlatch
	# !ide & d24 & ta6
	# rw & b1d24 & ieo & brst
	# !lint & rw & !a5 & ts6c & rcs;
   d24.CLK = ctclk;	// GCK
   d24.OE = d31_xcQ/d31_xcQ_TRST;    

d25.D = id9.PIN & idhlatch
	# !ide & d25 & ta6
	# rw & b1d25 & ieo & brst
	# !inta & rw & !a5 & ts6c & rcs;
   d25.CLK = ctclk;	// GCK
   d25.OE = d31_xcQ/d31_xcQ_TRST;    

d26.D = id10.PIN & idhlatch
	# !ide & d26 & ta6
	# rw & b1d26 & ieo & brst
	# !intb & rw & !a5 & ts6c & rcs;
   d26.CLK = ctclk;	// GCK
   d26.OE = d31_xcQ/d31_xcQ_TRST;    

d27.D = id11.PIN & idhlatch
	# !ide & d27 & ta6
	# rw & b1d27 & ieo & brst
	# !intc & rw & !a5 & ts6c & rcs;
   d27.CLK = ctclk;	// GCK
   d27.OE = d31_xcQ/d31_xcQ_TRST;    

d28.D = id12.PIN & idhlatch
	# !ide & d28 & ta6
	# rw & b1d28 & ieo & brst
	# !intd & rw & !a5 & ts6c & rcs;
   d28.CLK = ctclk;	// GCK
   d28.OE = d31_xcQ/d31_xcQ_TRST;    

d29.D = id13.PIN & idhlatch
	# !ide & d29 & ta6
	# rw & !a5 & ts6c & rcs
	# rw & b1d29 & ieo & brst;
   d29.CLK = ctclk;	// GCK
   d29.OE = d31_xcQ/d31_xcQ_TRST;    

d3.D = id3.PIN & idllatch
	# !ide & d3 & ta6
	# !lint & mski0 & iack6 & vect3
	# rw & b1d3 & ieo & brst
;Imported pterms FB4_9
	# !intd & mski4 & iack6 & vect3
	# !intc & mski3 & iack6 & vect3
	# !intb & mski2 & iack6 & vect3
	# !inta & mski1 & iack6 & vect3;
   d3.CLK = ctclk;	// GCK
   d3.OE = d7_xcQ/d7_xcQ_TRST;    

d30.D = id14.PIN & idhlatch
	# !ide & d30 & ta6
	# rw & !a5 & ts6c & rcs
	# rw & b1d30 & ieo & brst;
   d30.CLK = ctclk;	// GCK
   d30.OE = d31_xcQ/d31_xcQ_TRST;    

d31.D = id15.PIN & idhlatch
	# !ide & d31 & ta6
	# rw & !a5 & ts6c & rcs
	# rw & b1d31 & ieo & brst;
   d31.CLK = ctclk;	// GCK
   d31.OE = d31_xcQ/d31_xcQ_TRST;    

d31_xcQ/d31_xcQ_TRST = !ide & rw
	# rw & !a5 & ts6c & rcs
	# rw & !tap & ieo & brst;    

d4.D = id4.PIN & idllatch
	# !ide & d4 & ta6
	# !lint & mski0 & iack6 & vect4
	# rw & b1d4 & ieo & brst
;Imported pterms FB4_11
	# !intd & mski4 & iack6 & vect4
	# !intc & mski3 & iack6 & vect4
;Imported pterms FB4_13
	# !intb & mski2 & iack6 & vect4
	# !inta & mski1 & iack6 & vect4;
   d4.CLK = ctclk;	// GCK
   d4.OE = d7_xcQ/d7_xcQ_TRST;    

d5.D = id5.PIN & idllatch
	# !ide & d5 & ta6
	# !lint & mski0 & iack6 & vect5
	# rw & b1d5 & ieo & brst
;Imported pterms FB6_13
	# !intd & mski4 & iack6 & vect5
	# !intc & mski3 & iack6 & vect5
;Imported pterms FB6_15
	# !intb & mski2 & iack6 & vect5
	# !inta & mski1 & iack6 & vect5;
   d5.CLK = ctclk;	// GCK
   d5.OE = d7_xcQ/d7_xcQ_TRST;    

d6.D = id6.PIN & idllatch
	# !ide & d6 & ta6
	# !lint & mski0 & iack6 & vect6
	# rw & b1d6 & ieo & brst
;Imported pterms FB6_11
	# !intd & mski4 & iack6 & vect6
	# !intc & mski3 & iack6 & vect6
	# !intb & mski2 & iack6 & vect6
	# !inta & mski1 & iack6 & vect6;
   d6.CLK = ctclk;	// GCK
   d6.OE = d7_xcQ/d7_xcQ_TRST;    

d7.D = id7.PIN & idllatch
	# !ide & d7 & ta6
	# !lint & mski0 & iack6 & vect7
	# rw & b1d7 & ieo & brst
;Imported pterms FB6_7
	# !intd & mski4 & iack6 & vect7
	# !intc & mski3 & iack6 & vect7
;Imported pterms FB6_9
	# !intb & mski2 & iack6 & vect7
	# !inta & mski1 & iack6 & vect7;
   d7.CLK = ctclk;	// GCK
   d7.OE = d7_xcQ/d7_xcQ_TRST;    

d7_xcQ/d7_xcQ_TRST = !ide & rw
	# !intd & mski4 & iack6
	# !intc & mski3 & iack6
	# !inta & mski1 & iack6
	# !lint & mski0 & iack6
;Imported pterms FB10_1
	# rw & !tap & ieo & brst
;Imported pterms FB10_17
	# !intb & mski2 & iack6;    

d8.D = id8.PIN & idllatch
	# !ide & d8 & ta6
	# rw & b1d8 & ieo & brst;
   d8.CLK = ctclk;	// GCK
   d8.OE = d9_xcQ/d9_xcQ_TRST;    

d9.D = id9.PIN & idllatch
	# !ide & d9 & ta6
	# rw & b1d9 & ieo & brst;
   d9.CLK = ctclk;	// GCK
   d9.OE = d9_xcQ/d9_xcQ_TRST;    

d9_xcQ/d9_xcQ_TRST = !ide & rw
	# rw & !tap & ieo & brst;    

g0.D = Gnd;
   g0.CLK = pciclk;	// GCK
   g0.AP = !g0_OBUF/g0_OBUF_SETF__$INT;    

g0_OBUF/g0_OBUF_SETF__$INT = rst & !prst;    

!g1.D = !r1 & !g1
	# !r1 & r0 & !g0
	# !r1 & r0 & r4 & !g4
	# r0 & r4 & r3 & r2 & !g1
;Imported pterms FB16_12
	# !r1 & r0 & r4 & r3 & !g3
	# !r1 & r0 & r4 & r3 & r2 & !g2;
   g1.CLK = pciclk;	// GCK
   g1.AP = !g0_OBUF/g0_OBUF_SETF__$INT;    

!g2.D = !r2 & !g2
	# r1 & !r2 & !g1
	# r1 & r0 & !r2 & !g0
	# r1 & r0 & r4 & r3 & !g2
;Imported pterms FB16_9
	# r1 & r0 & r4 & !r2 & !g4
	# r1 & r0 & r4 & r3 & !r2 & !g3;
   g2.CLK = pciclk;	// GCK
   g2.AP = !g0_OBUF/g0_OBUF_SETF__$INT;    

!g3.D = !r3 & !g3
	# !r3 & r2 & !g2
	# r1 & !r3 & r2 & !g1
	# r1 & r0 & r4 & r2 & !g3
;Imported pterms FB16_7
	# r1 & r0 & !r3 & r2 & !g0
	# r1 & r0 & r4 & !r3 & r2 & !g4;
   g3.CLK = pciclk;	// GCK
   g3.AP = !g0_OBUF/g0_OBUF_SETF__$INT;    

!g4.D = !r4 & !g4
	# !r4 & r3 & !g3
	# !r4 & r3 & r2 & !g2
	# r1 & !r4 & r3 & r2 & !g1
;Imported pterms FB16_4
	# r1 & r0 & r3 & r2 & !g4
	# r1 & r0 & !r4 & r3 & r2 & !g0;
   g4.CLK = pciclk;	// GCK
   g4.AP = !g0_OBUF/g0_OBUF_SETF__$INT;    

!i6 = !intd & mski4
	# !intc & mski3
	# !intb & mski2
	# !inta & mski1
;Imported pterms FB2_9
	# !lint & mski0;
   i6.OE = i6_xcBUF/i6_xcBUF_TRST;    

i6_xcBUF/i6_xcBUF_TRST = !intd & mski4
	# !intc & mski3
	# !intb & mski2
	# !inta & mski1
	# !lint & mski0;    

iack6 = !mski0 & tt1.PIN & tt0.PIN & tm2.PIN & tm1.PIN & 
	!tm0.PIN
	# !mski1 & tt1.PIN & tt0.PIN & tm2.PIN & tm1.PIN & 
	!tm0.PIN
	# !mski2 & tt1.PIN & tt0.PIN & tm2.PIN & tm1.PIN & 
	!tm0.PIN
	# !mski3 & tt1.PIN & tt0.PIN & tm2.PIN & tm1.PIN & 
	!tm0.PIN
	# !mski4 & tt1.PIN & tt0.PIN & tm2.PIN & tm1.PIN & 
	!tm0.PIN;    

!icc0.T = !icc0 & !ta6
	# !icc0 & !icc2 & icc3 & !itf & !icc1;
   icc0.CLK = ctclk;	// GCK
   !icc0.AR = rst;	// GSR
   icc0.CE = ts6i;    

icc1.D = icc0 & !icc1 & ta6
	# !icc0 & icc1 & ta6;
   icc1.CLK = ctclk;	// GCK
   !icc1.AR = rst;	// GSR
   icc1.CE = ts6i;    

icc2.D = !icc0 & icc2 & ta6
	# icc2 & !icc1 & ta6
	# icc0 & !icc2 & !icc3 & icc1 & ta6
	# icc0 & !icc2 & !itf & icc1 & ta6;
   icc2.CLK = ctclk;	// GCK
   !icc2.AR = rst;	// GSR
   icc2.CE = ts6i;    

icc3.T = icc3 & !ta6
	# icc0 & icc2 & icc1 & ta6
	# icc0 & icc3 & itf & icc1
	# !icc0 & !icc2 & icc3 & !itf & !icc1;
   icc3.CLK = ctclk;	// GCK
   !icc3.AR = rst;	// GSR
   icc3.CE = ts6i;    

id0.D = d0.PIN & itr & ts6i
	# d0.PIN & a1 & ts6i & !long
	# d16.PIN & !a1 & !itr & ts6i;
   id0.CLK = ctclk;	// GCK
   id0.OE = !ide & !rw;    

id1.D = d1.PIN & itr & ts6i
	# d1.PIN & a1 & ts6i & !long
	# d17.PIN & !a1 & !itr & ts6i;
   id1.CLK = ctclk;	// GCK
   id1.OE = !ide & !rw;    

id10.D = d10.PIN & itr & ts6i
	# d10.PIN & a1 & ts6i & !long
	# d26.PIN & !a1 & !itr & ts6i;
   id10.CLK = ctclk;	// GCK
   id10.OE = !ide & !rw;    

id11.D = d11.PIN & itr & ts6i
	# d11.PIN & a1 & ts6i & !long
	# d27.PIN & !a1 & !itr & ts6i;
   id11.CLK = ctclk;	// GCK
   id11.OE = !ide & !rw;    

id12.D = d12.PIN & itr & ts6i
	# d12.PIN & a1 & ts6i & !long
	# d28.PIN & !a1 & !itr & ts6i;
   id12.CLK = ctclk;	// GCK
   id12.OE = !ide & !rw;    

id13.D = d13.PIN & itr & ts6i
	# d13.PIN & a1 & ts6i & !long
	# d29.PIN & !a1 & !itr & ts6i;
   id13.CLK = ctclk;	// GCK
   id13.OE = !ide & !rw;    

id14.D = d14.PIN & itr & ts6i
	# d14.PIN & a1 & ts6i & !long
	# d30.PIN & !a1 & !itr & ts6i;
   id14.CLK = ctclk;	// GCK
   id14.OE = !ide & !rw;    

id15.D = d15.PIN & itr & ts6i
	# d15.PIN & a1 & ts6i & !long
	# d31.PIN & !a1 & !itr & ts6i;
   id15.CLK = ctclk;	// GCK
   id15.OE = !ide & !rw;    

id2.D = d2.PIN & itr & ts6i
	# d18.PIN & !a1 & !itr & ts6i
	# d2.PIN & a1 & ts6i & !long;
   id2.CLK = ctclk;	// GCK
   id2.OE = !ide & !rw;    

id3.D = d3.PIN & itr & ts6i
	# d19.PIN & !a1 & !itr & ts6i
	# d3.PIN & a1 & ts6i & !long;
   id3.CLK = ctclk;	// GCK
   id3.OE = !ide & !rw;    

id4.D = d4.PIN & itr & ts6i
	# d20.PIN & !a1 & !itr & ts6i
	# d4.PIN & a1 & ts6i & !long;
   id4.CLK = ctclk;	// GCK
   id4.OE = !ide & !rw;    

id5.D = d5.PIN & itr & ts6i
	# d21.PIN & !a1 & !itr & ts6i
	# d5.PIN & a1 & ts6i & !long;
   id5.CLK = ctclk;	// GCK
   id5.OE = !ide & !rw;    

id6.D = d6.PIN & itr & ts6i
	# d22.PIN & !a1 & !itr & ts6i
	# d6.PIN & a1 & ts6i & !long;
   id6.CLK = ctclk;	// GCK
   id6.OE = !ide & !rw;    

id7.D = d7.PIN & itr & ts6i
	# d23.PIN & !a1 & !itr & ts6i
	# d7.PIN & a1 & ts6i & !long;
   id7.CLK = ctclk;	// GCK
   id7.OE = !ide & !rw;    

id8.D = d8.PIN & itr & ts6i
	# d24.PIN & !a1 & !itr & ts6i
	# d8.PIN & a1 & ts6i & !long;
   id8.CLK = ctclk;	// GCK
   id8.OE = !ide & !rw;    

id9.D = d9.PIN & itr & ts6i
	# d25.PIN & !a1 & !itr & ts6i
	# d9.PIN & a1 & ts6i & !long;
   id9.CLK = ctclk;	// GCK
   id9.OE = !ide & !rw;    

idhlatch.D = rw & !a1 & !itr & icc0 & icc2 & !icc3 & !itf & 
	!icc1 & ts6i
	# rw & !a1 & !itr & !icc0 & icc2 & !icc3 & itf & 
	icc1 & ts6i;
   idhlatch.CLK = ctclk;	// GCK    

idllatch.D = rw & itr & icc0 & icc2 & !icc3 & !itf & !icc1 & 
	ts6i
	# rw & itr & !icc0 & icc2 & !icc3 & itf & icc1 & 
	ts6i
	# rw & a1 & icc0 & icc2 & !icc3 & !itf & !icc1 & 
	ts6i & !long
	# rw & a1 & !icc0 & icc2 & !icc3 & itf & icc1 & 
	ts6i & !long;
   idllatch.CLK = ctclk;	// GCK    

ieo.T = bg60 & bb & ieo
	# !bg60 & bb & !brplx & !ieo;
   ieo.CLK = ctclk;	// GCK
   ieo.AR = plx/plx_RSTF;    

ior.T = ior & !icc0 & icc2 & !icc3 & !itf & icc1
	# ior & !icc0 & !icc2 & icc3 & itf & !icc1
	# rw & !ior & icc0 & !icc2 & !icc3 & itf & !icc1 & 
	ts6i
	# rw & !ior & !icc0 & !icc2 & !icc3 & !itf & !icc1 & 
	ts6i;
   ior.CLK = ctclk;	// GCK    

iow.T = iow & !icc0 & icc2 & !icc3 & !itf & icc1
	# iow & !icc0 & !icc2 & icc3 & itf & !icc1
	# !rw & !iow & icc0 & !icc2 & !icc3 & itf & !icc1 & 
	ts6i
	# !rw & !iow & !icc0 & !icc2 & !icc3 & !itf & !icc1 & 
	ts6i;
   iow.CLK = ctclk;	// GCK    

itf.T = a5 & d1.PIN & ts6c & !itf & rcs
	# a5 & !d1.PIN & ts6c & itf & rcs;
   itf.CLK = ctclk;	// GCK
   !itf.AR = rst;	// GSR    

itr.D = ta6.PIN & itr
	# ta6.PIN & icc0 & icc2 & !icc3 & !itf & icc1 & 
	ts6i & long
	# ta6.PIN & !icc0 & !icc2 & icc3 & itf & icc1 & 
	ts6i & long;
   itr.CLK = ctclk;	// GCK    

long = !siz1.PIN & !siz0.PIN;    

mski0.T = !rw & !a5 & d16.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!mski0 & ts6c & ieo & rcs
	# !rw & !a5 & !d16.PIN & !tsiz1.PIN & !a1 & !a0 & 
	mski0 & ts6c & ieo & rcs
	# !rw & !a5 & d16.PIN & tsiz1.PIN & !a1 & a0 & 
	!tsiz0.PIN & !mski0 & ts6c & ieo & rcs
	# !rw & !a5 & !d16.PIN & tsiz1.PIN & !a1 & a0 & 
	!tsiz0.PIN & mski0 & ts6c & ieo & rcs;
   mski0.CLK = ctclk;	// GCK
   !mski0.AR = rst;	// GSR    

mski1.T = !rw & !a5 & d17.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!mski1 & ts6c & ieo & rcs
	# !rw & !a5 & !d17.PIN & !tsiz1.PIN & !a1 & !a0 & 
	mski1 & ts6c & ieo & rcs
	# !rw & !a5 & d17.PIN & tsiz1.PIN & !a1 & a0 & 
	!tsiz0.PIN & !mski1 & ts6c & ieo & rcs
	# !rw & !a5 & !d17.PIN & tsiz1.PIN & !a1 & a0 & 
	!tsiz0.PIN & mski1 & ts6c & ieo & rcs;
   mski1.CLK = ctclk;	// GCK
   !mski1.AR = rst;	// GSR    

mski2.T = !rw & !a5 & d18.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!mski2 & ts6c & ieo & rcs
	# !rw & !a5 & !d18.PIN & !tsiz1.PIN & !a1 & !a0 & 
	mski2 & ts6c & ieo & rcs
	# !rw & !a5 & d18.PIN & tsiz1.PIN & !a1 & a0 & 
	!tsiz0.PIN & !mski2 & ts6c & ieo & rcs
	# !rw & !a5 & !d18.PIN & tsiz1.PIN & !a1 & a0 & 
	!tsiz0.PIN & mski2 & ts6c & ieo & rcs;
   mski2.CLK = ctclk;	// GCK
   !mski2.AR = rst;	// GSR    

mski3.T = !rw & !a5 & d19.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!mski3 & ts6c & ieo & rcs
	# !rw & !a5 & !d19.PIN & !tsiz1.PIN & !a1 & !a0 & 
	mski3 & ts6c & ieo & rcs
	# !rw & !a5 & d19.PIN & tsiz1.PIN & !a1 & a0 & 
	!tsiz0.PIN & !mski3 & ts6c & ieo & rcs
	# !rw & !a5 & !d19.PIN & tsiz1.PIN & !a1 & a0 & 
	!tsiz0.PIN & mski3 & ts6c & ieo & rcs;
   mski3.CLK = ctclk;	// GCK
   !mski3.AR = rst;	// GSR    

mski4.T = !rw & !a5 & d20.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!mski4 & ts6c & ieo & rcs
	# !rw & !a5 & !d20.PIN & !tsiz1.PIN & !a1 & !a0 & 
	mski4 & ts6c & ieo & rcs
	# !rw & !a5 & d20.PIN & tsiz1.PIN & !a1 & a0 & 
	!tsiz0.PIN & !mski4 & ts6c & ieo & rcs
	# !rw & !a5 & !d20.PIN & tsiz1.PIN & !a1 & a0 & 
	!tsiz0.PIN & mski4 & ts6c & ieo & rcs;
   mski4.CLK = ctclk;	// GCK
   !mski4.AR = rst;	// GSR    

!pcc0.T = !pcc0 & pcc2 & !pcc3 & !pcc1;
   pcc0.CLK = pxclk;	// GCK
   pcc0.CE = rw & ieo & psync & brst;    

pcc1.T = pcc0;
   pcc1.CLK = pxclk;	// GCK
   pcc1.CE = rw & ieo & psync & brst;    

pcc2.T = pcc0 & pcc1
	# !pcc0 & pcc2 & !pcc3 & !pcc1;
   pcc2.CLK = pxclk;	// GCK
   pcc2.CE = rw & ieo & psync & brst;    

pcc3.T = pcc0 & pcc2 & pcc1;
   pcc3.CLK = pxclk;	// GCK
   pcc3.CE = rw & ieo & psync & brst;    

pci = ;Imported pterms FB7_7
	  a30 & !a29
	# a30 & a31 & a27 & !a28;    

pcirst = rst & !prst;    

peot.D = !pcc0 & pcc2 & !pcc3 & ieo & !pcc1 & brst;
   peot.CLK = ctclk;	// GCK    

plx/plx_RSTF = !rst
	# bg60 & bb;    

prst.T = a5 & d0.PIN & ts6c & !prst & rcs
	# a5 & !d0.PIN & ts6c & prst & rcs;
   prst.CLK = ctclk;	// GCK
   !prst.AR = rst;	// GSR    

psync.T = rw & ieo & !psync & taend & brst;
   psync.CLK = ctclk;	// GCK    

pxclk.T = Vcc;
   pxclk.CLK = ctclk;	// GCK    

rcs = a30 & a31 & a29 & !a27 & !a28;    

shift.D = rw & pcc0 & !pcc2 & !pcc3 & ieo & brst
	# rw & !pcc2 & !pcc3 & ieo & pcc1 & brst;
   shift.CLK = pxclk;	// GCK    

!siz0 = !tsiz1.PIN & !brst;
   siz0.OE = !bb & ieo;    

!siz1 = !tsiz0.PIN & !brst;
   siz1.OE = !bb & ieo;    

!ta6.D = ts6p & !retry & ta6
	# ts6c & rcs & ta6
	# ts6p & !tap.PIN & teap & ta6
	# !intd & mski4 & iack6 & teap & retry & ta6 & 
	ts6bf
;Imported pterms FB7_4
	# !intc & mski3 & iack6 & teap & retry & ta6 & 
	ts6bf
	# !intb & mski2 & iack6 & teap & retry & ta6 & 
	ts6bf
	# !lint & mski0 & iack6 & teap & retry & ta6 & 
	ts6bf
;Imported pterms FB7_6
	# !inta & mski1 & iack6 & teap & retry & ta6 & 
	ts6bf
	# itr & icc0 & !icc2 & icc3 & itf & !icc1 & ts6i & 
	ta6 & long
	# itr & !icc0 & icc2 & !icc3 & !itf & icc1 & ts6i & 
	ta6 & long
	# !itr & icc0 & !icc2 & icc3 & itf & !icc1 & ts6i & 
	ta6 & !long
	# !itr & !icc0 & icc2 & !icc3 & !itf & icc1 & ts6i & 
	ta6 & !long;
   ta6.CLK = ctclk;	// GCK
   ta6.OE = ta6_xcQ/ta6_xcQ_TRST;    

ta6_xcQ/ta6_xcQ_TRST = !ieo & rcs
	# !ieo & pci
	# !intd & mski4 & iack6 & !ieo
	# !intc & mski3 & iack6 & !ieo
	# !inta & mski1 & iack6 & !ieo
;Imported pterms FB4_18
	# !intb & mski2 & iack6 & !ieo
	# !lint & mski0 & iack6 & !ieo;    

ta6cc0.D = !ta6cc0 & tea;
   ta6cc0.CLK = ctclk;	// GCK
   !ta6cc0.AR = rst;	// GSR
   ta6cc0.CE = ts6p & !ieo & pci & !ta6 & brst6;    

ta6cc1.D = ta6cc1 & !ta6cc0 & tea
	# !ta6cc1 & ta6cc0 & tea;
   ta6cc1.CLK = ctclk;	// GCK
   !ta6cc1.AR = rst;	// GSR
   ta6cc1.CE = ts6p & !ieo & pci & !ta6 & brst6;    

ta6m.D = !tap & ieo & !brst;
   ta6m.CLK = ctclk;	// GCK    

tacc0.D = !ta6.PIN & ieo & brst & !tacc0;
   tacc0.CLK = ctclk;	// GCK    

tacc1.D = !ta6.PIN & ieo & tacc1 & brst & !tacc0
	# !ta6.PIN & ieo & !tacc1 & brst & tacc0;
   tacc1.CLK = ctclk;	// GCK    

tacc2.D = !ta6.PIN & tacc2 & ieo & !tacc1 & brst
	# !ta6.PIN & tacc2 & ieo & brst & !tacc0
	# !ta6.PIN & tacc3 & !tacc2 & ieo & tacc1 & brst & 
	tacc0;
   tacc2.CLK = ctclk;	// GCK    

tacc3.D = !ta6.PIN & tacc3 & !tacc2 & ieo & brst
	# !ta6.PIN & tacc3 & ieo & !tacc1 & brst
	# !ta6.PIN & tacc3 & ieo & brst & !tacc0
	# !ta6.PIN & !tacc3 & tacc2 & ieo & tacc1 & brst & 
	tacc0;
   tacc3.CLK = ctclk;	// GCK    

taend.T = !tacc3 & !tacc2 & tacc1 & !taend & tacc0;
   taend.CLK = ctclk;	// GCK    

!tap.D = !tap & ieo & brst
	# !tap & ieo & !ta6m
	# !ta6.PIN & ieo & !brst & !ta6m
	# !tacc3 & !tacc2 & ieo & tacc1 & brst & tacc0;
   tap.CLK = ctclk;	// GCK
   tap.OE = ieo;    

tapcc0.T = Vcc;
   tapcc0.CLK = pxclk;	// GCK
   !tapcc0.AR = rst;	// GSR
   tapcc0.CE = ts6p & !tap.PIN & !ieo & pci & brst6;    

tapcc1.T = tapcc0;
   tapcc1.CLK = pxclk;	// GCK
   !tapcc1.AR = rst;	// GSR
   tapcc1.CE = ts6p & !tap.PIN & !ieo & pci & brst6;    

tea.D = !ts6p
	# teap & retry;
   tea.CLK = ctclk;	// GCK
   tea.OE = !ieo & pci;    

tm0 = Vcc;
   tm0.OE = !bb & ieo;    

tm1 = Gnd;
   tm1.OE = !bb & ieo;    

tm2 = Vcc;
   tm2.OE = !bb & ieo;    

ts6 = tsp.PIN;
   ts6.OE = !bb & ieo;    

ts6bf.D = !ts6.PIN;
   ts6bf.CLK = ctclk;	// GCK    

ts6c.D = a30 & a31 & a29 & !a27 & !a28 & ts6bf;
   ts6c.CLK = ctclk;	// GCK    

ts6i.D = ts6i & ta6
	# !ide & ta6 & ts6bf;
   ts6i.CLK = ctclk;	// GCK    

!ts6p.D = ieo
	# !a30 & !ts6p
	# !ts6p & !ts6bf
	# !ta6 & !brst6
;Imported pterms FB7_1
	# !a31 & a29 & !ts6p
	# a29 & !a27 & !ts6p
	# a29 & a28 & !ts6p
	# ta6cc1 & ta6cc0 & !ta6;
   ts6p.CLK = ctclk;	// GCK
   ts6p.AR = !ts6p/ts6p_RSTF__$INT;    

ts6p/ts6p_RSTF__$INT = rst & !prst & tea;    

tsiz0 = siz1.PIN & pci & !brst6;
   tsiz0.OE = !ieo;    

tsiz1 = siz0.PIN & pci & !brst6;
   tsiz1.OE = !ieo;    

tsp.D = tspm2
	# ts6.PIN & tsp;
   tsp.CLK = ctclk;	// GCK
   tsp.OE = !ieo;    

tspm.D = !tsp;
   tspm.CLK = ctclk;	// GCK    

tspm2.D = tspm;
   tspm2.CLK = ctclk;	// GCK    

tt0 = Gnd;
   tt0.OE = !bb & ieo;    

tt1 = Gnd;
   tt1.OE = !bb & ieo;    

ve4.T = !rw & !a5 & d4.PIN & tsiz1.PIN & a1 & a0 & 
	!tsiz0.PIN & !ve4 & ts6c & ieo & rcs
	# !rw & !a5 & d4.PIN & !tsiz1.PIN & a1 & !a0 & 
	tsiz0.PIN & !ve4 & ts6c & ieo & rcs
	# !rw & !a5 & d4.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!tsiz0.PIN & !ve4 & ts6c & ieo & rcs
	# !rw & !a5 & !d4.PIN & tsiz1.PIN & a1 & a0 & 
	!tsiz0.PIN & ve4 & ts6c & ieo & rcs
	# !rw & !a5 & !d4.PIN & !tsiz1.PIN & a1 & !a0 & 
	tsiz0.PIN & ve4 & ts6c & ieo & rcs
;Imported pterms FB12_18
	# !rw & !a5 & !d4.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!tsiz0.PIN & ve4 & ts6c & ieo & rcs;
   ve4.CLK = ctclk;	// GCK
   !ve4.AR = rst;	// GSR    

ve5.T = !rw & !a5 & d5.PIN & tsiz1.PIN & a1 & a0 & 
	!tsiz0.PIN & !ve5 & ts6c & ieo & rcs
	# !rw & !a5 & d5.PIN & !tsiz1.PIN & a1 & !a0 & 
	tsiz0.PIN & !ve5 & ts6c & ieo & rcs
	# !rw & !a5 & !d5.PIN & tsiz1.PIN & a1 & a0 & 
	!tsiz0.PIN & ve5 & ts6c & ieo & rcs
	# !rw & !a5 & !d5.PIN & !tsiz1.PIN & a1 & !a0 & 
	tsiz0.PIN & ve5 & ts6c & ieo & rcs
;Imported pterms FB12_17
	# !rw & !a5 & d5.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!tsiz0.PIN & !ve5 & ts6c & ieo & rcs
	# !rw & !a5 & !d5.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!tsiz0.PIN & ve5 & ts6c & ieo & rcs;
   ve5.CLK = ctclk;	// GCK
   !ve5.AR = rst;	// GSR    

ve6.T = !rw & !a5 & d6.PIN & tsiz1.PIN & a1 & a0 & 
	!tsiz0.PIN & !ve6 & ts6c & ieo & rcs
	# !rw & !a5 & d6.PIN & !tsiz1.PIN & a1 & !a0 & 
	tsiz0.PIN & !ve6 & ts6c & ieo & rcs
	# !rw & !a5 & !d6.PIN & tsiz1.PIN & a1 & a0 & 
	!tsiz0.PIN & ve6 & ts6c & ieo & rcs
;Imported pterms FB12_16
	# !rw & !a5 & d6.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!tsiz0.PIN & !ve6 & ts6c & ieo & rcs
	# !rw & !a5 & !d6.PIN & !tsiz1.PIN & a1 & !a0 & 
	tsiz0.PIN & ve6 & ts6c & ieo & rcs
	# !rw & !a5 & !d6.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!tsiz0.PIN & ve6 & ts6c & ieo & rcs;
   ve6.CLK = ctclk;	// GCK
   !ve6.AR = rst;	// GSR    

ve7.T = !rw & !a5 & d7.PIN & tsiz1.PIN & a1 & a0 & 
	!tsiz0.PIN & !ve7 & ts6c & ieo & rcs
	# !rw & !a5 & d7.PIN & !tsiz1.PIN & a1 & !a0 & 
	tsiz0.PIN & !ve7 & ts6c & ieo & rcs
	# !rw & !a5 & d7.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!tsiz0.PIN & !ve7 & ts6c & ieo & rcs
	# !rw & !a5 & !d7.PIN & tsiz1.PIN & a1 & a0 & 
	!tsiz0.PIN & ve7 & ts6c & ieo & rcs
	# !rw & !a5 & !d7.PIN & !tsiz1.PIN & a1 & !a0 & 
	tsiz0.PIN & ve7 & ts6c & ieo & rcs
;Imported pterms FB12_14
	# !rw & !a5 & !d7.PIN & !tsiz1.PIN & !a1 & !a0 & 
	!tsiz0.PIN & ve7 & ts6c & ieo & rcs;
   ve7.CLK = ctclk;	// GCK
   !ve7.AR = rst;	// GSR    

vect0.D = !lint
	# !intb & inta
	# !intd & intc & inta;
   vect0.CLK = ctclk;	// GCK    

vect1.D = !intb & lint
	# !inta & lint;
   vect1.CLK = ctclk;	// GCK    

vect2.D = !intd & intb & inta & lint
	# !intc & intb & inta & lint;
   vect2.CLK = ctclk;	// GCK    

!vect3.D = intd & intc & intb & inta & lint;
   vect3.CLK = ctclk;	// GCK    

!vect4.D = !ve4
	# intd & intc & intb & inta & lint;
   vect4.CLK = ctclk;	// GCK    

!vect5.D = !ve5
	# intd & intc & intb & inta & lint;
   vect5.CLK = ctclk;	// GCK    

!vect6.D = !ve6
	# intd & intc & intb & inta & lint;
   vect6.CLK = ctclk;	// GCK    

!vect7.D = !ve7
	# intd & intc & intb & inta & lint;
   vect7.CLK = ctclk;	// GCK    

******************************  Device Pin Out *****************************

Device : XC95288XL-7-TQ144


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 VCC                              73 VCC                           
  2 d0                               74 id2                           
  3 d1                               75 id12                          
  4 d2                               76 id3                           
  5 d3                               77 id11                          
  6 d4                               78 id4                           
  7 bi                               79 id10                          
  8 VCC                              80 id5                           
  9 tap                              81 id9                           
 10 tsp                              82 id6                           
 11 burst                            83 id8                           
 12 retry                            84 VCC                           
 13 ide                              85 id7                           
 14 i6                               86 ccs                           
 15 bs0                              87 g0                            
 16 bs1                              88 r0                            
 17 bs2                              89 GND                           
 18 GND                              90 GND                           
 19 bs3                              91 r4                            
 20 tt1                              92 r3                            
 21 tt0                              93 g4                            
 22 tm2                              94 g3                            
 23 tm1                              95 g2                            
 24 tm0                              96 r2                            
 25 ieo                              97 g1                            
 26 br60                             98 r1                            
 27 brslt                            99 GND                           
 28 bg60                            100 pcirst                        
 29 GND                             101 inta                          
 30 ctclk                           102 intb                          
 31 bgslt                           103 intd                          
 32 pciclk                          104 intc                          
 33 ts6                             105 d31                           
 34 bb                              106 d30                           
 35 rw                              107 d29                           
 36 GND                             108 GND                           
 37 VCC                             109 VCC                           
 38 pxclk                           110 d28                           
 39 tsiz1                           111 d27                           
 40 tsiz0                           112 d26                           
 41 siz1                            113 d25                           
 42 VCC                             114 GND                           
 43 bdip                            115 d24                           
 44 siz0                            116 d23                           
 45 tea                             117 d22                           
 46 ta6                             118 d21                           
 47 GND                             119 d20                           
 48 a31                             120 d19                           
 49 a30                             121 d18                           
 50 a29                             122 TDO                           
 51 a28                             123 GND                           
 52 a27                             124 d17                           
 53 a5                              125 d16                           
 54 a1                              126 d15                           
 55 VCC                             127 VCC                           
 56 a0                              128 lint                          
 57 KPR                             129 d14                           
 58 cs1                             130 d13                           
 59 cs0                             131 d12                           
 60 KPR                             132 d11                           
 61 ior                             133 d10                           
 62 GND                             134 d9                            
 63 TDI                             135 teap                          
 64 iow                             136 bgplx                         
 65 TMS                             137 d8                            
 66 id15                            138 brplx                         
 67 TCK                             139 d7                            
 68 id0                             140 d6                            
 69 id14                            141 VCC                           
 70 id1                             142 d5                            
 71 id13                            143 rst                           
 72 GND                             144 GND                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95288xl-7-TQ144
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : ON
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25