December 2011 to
January 2012
After
a long break (sorry !), hardwre tests and many hardware bugs removed in the
CPLD (and the 2 CT60 CPLD for local bus arbitration again).
The
PCI arbiter is re-designed and now USB board is running on PCI bus with
Radeon.
The
IDE port is now OK too. The Interupts run too.
PLX
DMA read in SDRAM seems OK and is used by VDI
USB
is not yet finished...
April 2010 to
September 2010
Design
and tests for the software and many hardware bugs removed in the CPLD (and
the 2 CT60 CPLD for local bus arbitration).
The
Radeon card is running fine but the use of other PCI baords is not possible.
A problem on the CPI bus ?
March
2010, 3rd
I
soldered an osc. from my stock (an old plastic DIP model) on a CTPCI board
and it runs 100% well with the Radeon PCI.
Ouf,
the PCB is bug free...
I
will transfer the SMT osc. from the prototype to a new board and send this
board to didier to let him work with the software.
The
assembling compnay is now urged to find a part and financial solution with
the part furnisher that did the mistake. I should get news this day or
tomorrow.
March
2010, 2nd
Control
of the oscillator on an other board : hum, it's strange, the pin #2 & 4
(GND & VDD) are connected together inside the osc. This explains well
the smoke....
It
seems so that the parts funisher of the assembling company did a mistake
about the model of oscillator and did not take account about my osc.
reference/manufacturer list with a standard pin-out (CTS & Fox
references).
March
2010, 1st
I
spent a bit time with the CPLD source to try to finish the PLX BURST Read
from SDRAM.
Yes
! I get the boards and it's beautifull !
First
power on test and.... it's smoking on the 33 MHz oscillator... Aie !
The
33 MHz oscillator for PCI seems to be inversed on PCB. I move it by 180°.
Smoke
again !
February
2010
The
PCB are come back to the assembling company and I have to bring some parts (connectors)...
Visit
at the assembling company and last layout recommendations to avoid an
assembling mistake.
January
2010
The
2 boards PCB are now in production phase and the assembling company is
receiving the parts.
It
seems there is no problem with the PCB files reading on the CAD system.
December
2009
PCB
routing modifications on the 2 boards to be compatible with 80 wires IDE
flat cables.
Sent
of the files to the PCB manufacturer for files control on their CAD system.
Unfortunately,
they close on the last week of the month. It will be for January 2010 now.
The
PLX transfers now with DMA (060 bus master) with read & write but only
with single accesses; the burst read is not yet running.
September
2009, 1st
CTPCI
orders are open.
Stills
the PLX DMA and the IDE accesses to be tested and debugged.
August
2009, 21th
Running
fine with 2 flat cables 80-wires of 45 cms long.
I
secured timing on CTPCI and ABE/SDR chips.
Now, the
timing limit of chips is far above 100 Mhz...
The only
frontier to overclock more than 100 Mhz is the 060 and its cooling quality.
Those of
you that were not able to overclock after 105 or 107 Mhz may have a very
nice surprise...
The
world record is 108 MHz without CTPCI . Mine is at 105 Mhz + CTPCI and
with the standard CT63 low profile cooler...
Other
news, the 060 BURST with MOVE16 instruction is working...
Stills
to be tested :
- PLX
master for DMA
-
Interupts
- IDE port
I
can launch some software in 1027*768* 256c or TC...
Good
news : Cubase Audio
2.6 runs fine in these resolutions !
August
2009, 13th
Second
day of running CT60 + CTPCI at 100 Mhz and what a pleasure to see the
first benchs with Kronos
en 640*480*256c et en 1024*768*TC and a big desktop !
Didier
did a great work on VDI if you see the new VDI that is 10 times faster
than with a CT60-100/25Mhz and 7 times faster than with the (now very) old
Hades 060 ...
I
did some successfull tests with 2 flat cables of 30 cms (40 wires) instead
of the two of 10 cms I was using so far... I have to test the 80 wires
flat cables that offering better performances (and more easy to find ), so
I'm confident...
I
have now to test the BURST of the 060 with the famous MOVE16 instruction
and I just received the test software from Didier (yeah, we may increase
the benchs !).
I
get too the new tos from Didier that use the DMA from PLX to transfert
data from SDRAM to Video DDR. I will be able to test the famous old CT60
arbiter (tested only with Blitter and SDMA chips so far...).
August
2009, 12th
A
few days of brainstorming and some new tests witht he logic analyser to
persuade me that the essential of the problems are coming from the clokcs
and precisely from the cypress PLL chip that divide by 2 the CT clock for
PLX.
I
have unsolder it and connected directly the CT clock to CPLD and used CPLD
to divide the CT clock. The CPLD get a delay of around 5 ns on the new PLX
clock.
But
the CTPCI is now running perfectly at 66 Mhz and all tests are good. The
radeon is running fine ! No more crash.
I
now boot at 95 Mhz but it stills some timing problems I have to correct in
the CPLD.
We
will nextly be able to test the PLX DMA.
July 2009,
19th
Yeah,
we got it, the first
screen from the Radeon board. It seems we get some problems with BIOS
reading and finally the last problems were PLL initialization.
We
don't know why but the VGA BIOS is not writting the PLL registers...
Didier
forced the good data to PLL registers...without BIOS and it runs now...
OK
we have bus
error before the desk but that is not important... ;-)
July 2009,
16th
After
2 weeks of trying to speak with the PLX we successed the PLX registers
reading & writing.
Actually
tests show that we can run the CT60 up to 85 MHz with a good link with CTPCI.
PLX9054 is not able to run
above 50 Mhz, it is why my logic is controlling a CT60 CLK/2 clock for PLX..
Sure
the PCI is independant with 33 Mhz.
The
final tests will be to go to 100/50 Mhz stable configuration.
BUT actually, after 10 days
of stress and tests we are not able to communicate well with the Radeon
board.
Oh, sure the PCI BIOS scan
is working fine and find the board with it's ATI ID...in all the 4 slots
and we can access to the PCI registers of the Radeon.
But when we load the BIOS
ROM from ATI and lauch the X86 emulator, the things are bad...: master
aborts and parity errors are coming and/or the X86 code is bad.
We reduced PCI flat cables
to 10 cms and downgraded the PCI clock to 16 Mhz, with same results...
what let me think this damned PCI bus is good and
there is a software vicious bug or a not completed Radeon init...
A good news is that there
is only 2 minors modifications on the CTPCI prototype and 1 minor
modification on PCI slots board...if we have no more hardware bug
discovered...
I have only to pay 2 new
films for first batch production.
Next news should be the
good ones...
June 2009,
19th
One week
ago I get the last components and I just finished now to assemble the boards.
First
good news : no mecanical errors; all is fitting perfectly on CT60.
Some
pictures before I power on, begin the electrical controls and launch the
software.
March 2009
New
design of CTPCI
:
- Add an
IDE port (mode PIO4) 100% compatible & 50 % faster than the Falcon one
(PIO3 with Combel) with
logic registers to optimize the tranfer timings according to the
CT60/63 clock speed. Sorry, one wire must be connected on falcon motherboard
to use this IDE port. It will be possible to use the 2 IDE ports for 4
devices.
- New
CPLD with twice logic (288 registers). The transfers of PLX reads (from
SDRAM) are now supported with BURST. The writes of the PLX (into SDRAM) are
not supported as BURST because of the clock difference between PLX &
CT60/63 (PLX clock is divided by 2).
- Remove
the
drive 5 1/4 power connector
New
design of PCI
4 Slots :
- Change
dimensions for a better fitting into PC towers.
- Change
routing from 4 layers to double face PCB to reduce cost.
- New atx
holes drilling.
December 5th,
2008
Adding a
drive 5 1/4 power connector on the main and PCI slots boards.
Adding a
5 to 3.3V 4A voltage linear regulator on the PCI Slots board.
Adding
the fitting holes on the PCI slots board.
October 28th,
2008
Routing
is finished. Verifications are OK. Next step : prototype.
September
2008
Autorouter
try : 97.4% of 1138 nets. Stills some settings to be done, some manual PCB
work, some parts to be validated and tuning of the clocks traces.
September
2007 to March 2008
The
hierarchical schematics are finished. This design method allows the reuse of
some blocks in some others designs... I will so continue to layout of the
boards with need to create some parts in the library... I present you
the 'TOP' sheet of the CTPCI project : the blocks point to schematics sheet.
Here is the PLX
sheet.
August
2007
Happy
getting a bit money to buy some parts to assemble a powerfull PC in my week
appartement to run Dx Designer & Pads Layout + Router software flow from
Mentor Graphics. I get a licence that costs 6000...
January to
June 2007
The
project is going slowly because of my job far from my house and so some
heavy days and shorts week ends... Finally I finished the design of the CPLD
and I will go back to schematics.
September 2006
After a
long period very busy, I go back on CTPCI design...
I try to
find a better CAD software to boost the PCB design.
May 2006
Thought
about a new IDE port : negative (no place & may be available on PCI).
April 2006
Deepened
study of the PLX 9054 to determine the logic conception with the CT bus.
Study
the PCI-->Local (PCI master & DMA) data transfert rates according to
the technical choices for the 'glue' logic : CPLD or FPGA.
March 2006
Project on
the rails again.
PCI
knowledges refresh.
Start the
writing of the developers documentation (CTPCI Hardware Guide).
November
2005
Confirmation
the project can be developed.
Project
stopped.
August 2005
Announcement
of the project and opinion testing among the CT users.
