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9.12 CAC-Interface
FDI modifications
Well after opening the CAC there is simply a crystal (to give CAF
a 44.1KHz sample rate) an IC and some resistors. One would have to
take the Word Clock signal and change it to what the Falcon needs.
Since I have an FDI, I don't need the CAC.
But how to change the Word Clock? in fact what are the specs for
WordClock I do know something about it being TTL level etc... These
are the frequencies that the Falcon needs to get 44.1, 48 etc.
Master clock Divisor(n) Bit Rate Sample Rate --------------------------------------------------------- 25.175 MHz 4 6.29375 MHz 49.17 KHz (50KHz) 22.5792 MHz 4 5.6448 MHz 44.1 KHz (CD) 24.576 MHz 4 6.144 MHz 48.0 KHz (DAT) 32.000 MHz 4 8.000 MHz 62.5 KHz --------------------------------------------------------- Now the trick is to get Word Clock to a MHz freq and then just put
in a switch where the new signal will replace the internally available
sample rates.
After getting confused I got a Z-1SRC Sample Rate converter that
locksto Word Clock, also Ardvark? makes a master Word Clock generator.
It seems simple enough though.
Here is a file on the audio matrix of the Falcon. The last part
has a pin out (of the DSP) to the Steinberg DB15, in case your cable
gets damaged.
Overview Of The Falcon030 DSP & Audio System
(from documentation by Atari Corp. dated October 1, 1992) The Atari Falcon030 contains a sophisticated digital processing
and audio sub-system...
32 MHz 56001 Digital Signal Processor with 96K bytes of zero
wait-state SRAM.
Eight track, 16-bit digital DMA record channel.
Eight track, 16-bit digital DMA playback channel
On-board 16-bit stereo DACs, feeding the internal loudspeaker and
headphone jack.
On-board 16-bit stereo ADCs, and stereo microphone jack.
Sophisticateddata path matrix between DSP, DMA, Codec and external
connector.
Sample rates up to 50KHz.
Serial data transfer rates up to 1MByte per second.
Loudspeaker or headphones can monitor any stereo channel of 8
track digital playback data.
External serial record and playback channels connect to industry
standard DACs, ADCs and S/PDIF components with minimum additional
logic.
The block diagram on the following page describes the Digital
processing sub-system.
Address Bus
===================================|===========================|=============
Data Bus /|\ /|\
===================================|===========================|=============
^ ^ | | |
| | | | |
| | | | |
| ---|--------\|/--------------v----------\|/--------
____|__ | _|_________|_______ __|___________|_______ |
________ | Host | | | FIFO | DMA Record | | FIFO | DMA Playback ||
| | | | | | | | | | ||
|32k x 24|_| 56001 | | |______|____________| |_______|______________||
| SRAM | | SSI | | | Control | | Control ||
| | | | | | | | ||
-------- |_______| | |___________________| |______________________||
^ | | ^ | |
| | | | | |
| | | _______|_________________________v____________ |
| |------>| |<----
| | | | || |
|<---------| || |
| | | | Multiplexer & Protocol Converter || | |
| | ---->| || | |
| | | _|__| || | |
| | | || | || | |
| | | || |______________________________________________|| | |
| | | ||______|______|______|___________________|_________| | |
| | | | | | | | | |
| | | | | 25.175 32.0 Sample Clk | | |
| | | | | MHz MHz ____v____ | |
| | | | __| _________| DAC |<----- |
I/O interupt| | | | | | |_________| |
^ ^ | | | | | | -->| ADC |<--------
|/3 | | | | | | | | |_________|
/ | | | | | | | | ^
/| | | | | | | | | |___PSG
_v_____|____|__v_|_v____|____ Phones Mic
| |
| DSP Connector |
|_____________________________|
The digital processing sub-system has many features which make it
ideal for audio processing. However, the data being processed can also
be video (images), graphics objects (3-D image manipulation) or any
other general purpose data.
To maintain the maximum flexibility, the Atari Falcon030 provides
an extremely general connection system between these components. All
data transfers are in a synchronous serial format. Any component can
talk with any other. Since some of the components have real time
response requirements, the clocking schemes have also been made
especially general and flexible.
Communications
1) Connect the two devices (a receiving device to a source device) 2) Select the source clock 3) Select the communication protocol (handshake or continuous) Connections
There are four devices capable of sending data and four devices
capable of receiving data. To allow any connection therefore requires
a four by four matrix:
Source Device
_________________
|Ext Input Channel|--------O---------O----------O----------O
----------------- | | | |
_________________ | | | |
| DSP Transmit |--------O---------O----------O----------O
----------------- | | | |
_________________ | | | |
| DMA Playback |--------O---------O----------O----------O
----------------- | | | |
| | | |
L Mic | | | |
---------- ___ | | | |
PSG--<======= <|--*-----O---------O----------O----------O
__________ --- (ADC)| | | | |
R Mic | | | | |
| | | | |
_|_____|_ ____|____ ____|____ ____|______
\ / | DSP || DMA ||Ext Output |
\ + / | Recieve || Record || Channel |
----- --------- --------- -----------
|
_|_
\_/ (DAC)
|
|
/ \
/ \
Phones Speaker
Each receiving device can have its data path connected to any one
source device. Source devices "source" data. For example,
the ADC represents data from the microphone jack so the ADC is a data
source. It can send it's data to any (or all) receiving devices. See
the "Devices" section for more details.
Clock Sources
All the data connections shown above, are actually serial data
paths which include a bit clock, data, and synchronization signal.
There are three possible clock sources in the system:
Internal clock (25.175 MHz) Internal clock (32 MHz) External clock Each source device must select one of these clocks as its master
clock. The Codec can only use the Internal 25.175MHz, or External
clock. The bit clock is taken from the master clock divided by a
programmable value of 4 to 24 (in increments of 4). The Sample rate is
then the bit rate, divided by 128:
___________ ___________
Master Clock | Divide by | Bit Rate | Divide by | Sample
Rate | | | |
--------------->-----| n |-------->------| 128 |------->-------
----------- -----------
Since the bit rate is 128 times the sample rate, there is room for eight 16-bit samples per sample period.(!nl) Master clock Divisor(n) Bit Rate Sample Rate --------------------------------------------------------- 25.175 MHz 4 6.29375 MHz 49.17 KHz (50KHz) 22.5792 MHz 4 5.6448 MHz 44.1 KHz (CD) 24.576 MHz 4 6.144 MHz 48.0 KHz (DAT) 32.000 MHz 4 8.000 MHz 62.5 KHz --------------------------------------------------------- The internal 25.175 MHz clock is used to support STE compatible
50KHz, 25KHz, and 12.5KHz sound sample rates. (Note that the built in
DACs do not actually support a 6.25KHz sample rate) The internal 32
MHz clock is useful since it can be used to provide an 8 MHz bit rate
(or 1 Megabyte per second), which is the maximum transfer rate of the
DSP SSI interface.
The external clock comes from the DSP connector. It can run up to
32 MHz. Some useful external clock rates are shown below:
Communications Protocols
If the data is sound data and it is not critical, then an
occasional overrun or underrun may be acceptable. If the data is JPEG
video, DSP object code, or any other non redundant data, then you wlll
want to guarantee it is never mislaid.
For precisely this purpose our system includes a special
handshaking mode which prevents overrun or underrun. When in
handshaking mode, the data rate can be variable since timely bus
access cannot be guaranteed. This also means that in handshaking mode
there is no concept of a sample rate, or left and right tracks, or
multiple tracks at all. The data is simply transferred one word at a
time as quickly as the source and receiving devices can communicate.
Devices
Device Data Source Data Receiver --------------------------------------------- DMA DMA Playback DMA Record Codec ADC DAC DSP DSP Transmit DSP Receive External Ext Input Ext Output These devices can be connected together in a very flexible manner
(as shown in the matrix under "Connections" earller in this
section). Each device has its own special characteristics, which are
described below.
The DMA input channel provides a fast path to system memory.
Briefly, it includes a 32 byte FIFO on the data path synchronized with
a memory addressing module which can fill memory in a linear,
continuous or looping mode. The maximum data transfer rate is about
one Megabyte per second.
The data and clock signals to DMA input must be synchronized.
Source devices can send data to DMA input in either handshaked or
non-handshaked modes.
In handshaked mode DMA Input must be the clock source. It uses a
gated clock technique to stop data transmission if its FIFO becomes
full.
In non-handshaked mode, DMA input receives a clock from the
sending device. When its FIFO becomes half full it will attempt to
write it to memory. If it cannot get access to the system bus in time,
data will overflow.
Non-handshaked mode to DMA input is provided simply because it puts less burden on the sending device. However, when using it the user must be careful to limit the data transfer rate to within system bus bandwidth limits. DMA Output
Non-handshaked mode is normally used for communication with DACs
or other real-time devices. If the system bus becomes overloaded for
any reason with higher priority bus masters data may be lost in
non-handshaked mode.
As usual, the receiving device must be using the same clocks and
protocol as DMA output to ensure correct data transfer.
Digital Signal Processer (DSP)
The Atari Falcon030 includes a Motorola 56001 Digital Signal
Processor. This part offers the following features:
32 MHz operation, yields 96 MOPS. 1024 point complex FFT can be done in 2.07 imlliseconds. 24 bit internal and external data paths, yielding 144 dB dynamic range. 56 bit accumulators. The following operations can be executed in parallel in one instruction cycle: 24 x 24 multiply 56 bit addition Two data moves Two address pointer updates Instruction prefetch 1024 x 24 bits of on chip RAM. 512 x 24 bits of on chip ROM used for Mu-Law, A-Law and four quadrant Sine wave table data. DSP Memory Map
In addition to the on-chip RAM and ROMs there are 32K words of
external, zero wait state SRAM. The memory map is conflgnred as
follows:
Program space is one contiguous block of 32K words.
X and Y data space are each separate 16K word blocks. Both X and Y
can be accessed as blocks starting at 0 or 16K. Program space
physically overlaps both X and Y data spaces.
Note that since program space overlaps X and Y space DSP software
must becareful to avoid having program and data memory corrupt each
other. Note that X:0, X:16K and P:16K are the same physical RAM
location, and that Y:0, Y:16K and P:0 are also at the same physical
RAM location.
$ffff _____________ ______________ _____________
| | | | | |
| Reserved | | Reserved | | Reserved |
| | | | | |
$7fff |-------------| |--------------| |-------------|--------
| 16 K | | 16 K | | 32 K |Overlaps
| Shadow | | Shadow | | Program |Xmemory
|-------------| |--------------| | RAM |--------
$3fff | 16 K | | 16 K | | |Overlaps
|External RAM | |External RAM | | |Ymemory
$01ff |-------------| |--------------| |-------------|--------
| Internal | | Internal | | Internal |
| RAM/ROM | | RAM/ROM | | RAM |
$0000 |_____________| |______________| |_____________|
X Memory Y Memory P Memory
SSI Interface
The Atari Falcon030 brings out the six wire SSI port to the
external DSP connector.
Host Port
Interface with the 68030 host is via the 56001 host port (port B).
Data transfer by the host is via programmed I/O. In other words, the
DSP host port appears in the 68030 memory map as eight byte locations,
Data transfers by the host should always be conducted thruogh the
appropriate operating system calls (see the Atari Falcon030 software
developers guide). DSP software transfers data to and from the host
port in the usual way (see 56001 DSP Users Manual). The host can
interrupt the DSP and vice-versa.
SCI
DSP Expansion Port
This DB26 female connector includes a variety of signals designed
primarily for the connection of digital sound devices and modems. It
can (and almost certainly will) be used for a number of other
appllcations such as low cost laser printers, video digitizers,
scanners and so forth.
The pinout is as follows:
DSP Connector, DB26, three row female: Pin# Signal Pin# Signal Pin# Signal --------------------------------------------------------- 1 GP0 10 GND 19 R_DATA * 2 GP1 11 SC0 20 R_CLK 3 GP2 12 SC1 21 R_SYNC 4 P_Data 13 SC2 22 EXT_INT 5 P_CLK 14 GND 23 STD 6 P_SYNC 15 SRD 24 SCK 7 n/c 16 cRD 25 GND 8 GND 17 +12v 26 EXCLK 9 +12v 18 GND -------------------------------------------------------- * pin 19 was not listed in the document I read. Pin Description: CP(2:0) I/O General purpose inputs and outputs. Can be individually set and read EX-INT I General purpose interrupt input -------------------------------------------------------- SC0 I/O DSP SSI port Pin SC0 (PC3), Receive clock SC1 I/O DSP SSI port Pin SC1 (PC4), Receive Sync SC2 I/O DSP SSI port Pin SC2 (PC5), Transmit Sync SCK I/O DSP SSI port Pin SCK (PC6), Transmit clock SRD I/O DSP SSI port Pin SRD (PC7), Receive Data STD I/O DSP SSI port Pin STD (PC8), Transmit data XO_DATA O External Serial Output, serial data XO_CLK O External Serial Output, serial clock XO_SYNC I/O External Serial Output, Sync XI_DATA I External Serial Input, serial data XI_CLK O External Serial Input, serial clock XI_SYNC I/O External Serial input, Sync EX_CLK I External master clock +12v- +12v power. Do not draw more than 300mA on this pin. The signals on this port include several high speed clock and data
lines. It is therefore essential that developers use correct drive and
termination. In general, all signals should be terminated with a
ferrite bead followed by a 68ohm resistor in series. This is the same
type of termination used inside the Atari Falcon030 on all DSP port
signals. A ferrite bead should be chosen that does not begin cutoff
until 20MHz to 30MHz. Input signals from the peripheral should be
driven by CMOS devices such as 74HCxx or 74HCTxx.
Total cable length should not exceed 24 inches and we strongly
advise the use of twisted pair cables.
General Purpose Bits
DSP SSI Interface
These six pins are the SSI port from the Motorola 56001 DSP chip.
The serial clock can operate up to one quarter of the 32 MHz DSP
master clock rate, or 8MHz. To use these pins to talk directly with
the DSP you need to take care to avoid contention with the
communication matrix by tri-stating the communication matrix outputs
through the appropriate OS call.
External Serial Output channel
This three wire serial interface can be used to transfer data from
the host computer. It can transfer data from the DSP, DMA playback
channel, or on board analogne to digital convertor.
Data transfers use either continuous mode or a handshaked (gated
clock) mode:
Signal Continuous Handshaked --------------------------------------------- XO_DATA Output Output XO_CLK Output Output XO_SYNC Output Input --------------------------------------------- In either mode, data changes on fhe rising edge of the clock. Data
should be sampled on the falling edge of the clock.
In Continuous mode there are 128 clock cycles per sample period.
XO_SYC will go high for the first 16 bits of a sample period and then
low for the remaining 96 bits. In each sample period a maximum of 8
tracks of 16 bit data can be transferred. Data words are transmitied
MSB first, end-on-end, with no gaps in between them. The number of
words per sample period is determined by the source device.
A typical sample is shown below:
128 Clock Cycles
|<-------------------------------------------------------------------->||
|___ ___ |___ |___ ___ ___ |___ |___ CLK |___
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | |
| |__| |__| |__| |__| |_.._| |__| |__| |_............__| |_|
|-------------------------------------------:--- SYNC |-----
| : | | : |___________________|
| : | |
| : | DATA |
| _____ _____ _____ ................... _____ |_____ ...........|
|\/ MSB \/ \/ \/ \/ LSB \/ MSB \/ |
|/\_____/\_____/\_____/\................... /\_____/\_____/\...........|
| : | <-------->
| |Word 2 Word 16|Wrd 1
=============================================================================
DATA & SYNC change on rising edges of CLK & should be
sampled on failing edges of CLK
In Handshaked mode XO_SYNC becomes an input. The external device
will pull XO-SYNC high, and if the source device is ready, XO_CLK will
become active for 16 cycles (or one word) together with XO_DATA.
XO_SYNC is sampled by the source device at the end of each word. If
XO_SYNC is high and another word is ready to be sent, XO_CLK and
XO_DATA will become active for another 16 cycles. A minimum of two
clock periods will always be inserted between data words.
This gated clock technique will prevent overrun or underrun at
either end of the data paths:
|___ ___ ___ ___ ___ ___ ___ ___ CLK |___
| | | | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | | |
_| |__| |__| |__| |__| |_.._| |__| |__| |_............__| |_|
-------------------------------------------------- SYNC|-----| |
|
DATA |
_____ _____ _____ ................... _____ _____ ........... |
\/ \/ \/ \/ \/ \/ \/
/\_____/\_____/\_____/\................... /\_____/\_____/\.......... ./|
One Word |
Note: SYNC hold time after first rising edge of CLK = 0ns
=============================================================================
External Serial Input Channel
This three wire serial interface can be used to transfer data to
the host computer. It can transfer data to the DSP, DMA record
channel, or an on board digital to analogne convertor. Data transfers
use either conimuous mode or a handshaked (gated clock) mode:
Signal Continuous Handshaked --------------------------------------- XI_DATA Input Input XI_CLK Output Output XI_SYNC Output Input --------------------------------------- In continuous mode it is the responsibdity of the external device
to synchronize to the XI_CLK and XI_SYNC outputs. Data should be
changed on the rising edges of XI_CLK since it will be sampled on the
falimg edges. XI_SYNC will identify the start of a frame by going high
for the first 16 clock cycles, and then low for the remaining 96
cycles. In handshaked mode the protocol is basically the same as for
the external serial output channel, except that XI_DATA is an input.
When the external device has no data to send it must pull XI_SYNC low
at least one clock cycle before the end of the previous sample.
External Master clock
CODEC
The Atari Falcon030 on board Codec is a high performance, 16 bit,
stereo device. It includes a stereo DAC and stereo ADC.
16-bit Stereo DAC
Stereo Headphone Jack
The output port is a voltage drive with a peak voltage level of
3v, and an RMS level of 2v. It is designed for a peak load of 0.25W;
this means that the load should have an impedance greater than 32ohms.
________/\/\/\/\______
|1 |
| |
6||| |
|||8 ===
|\|| | 0.033UF
3 | \| |
_/\/\/\_____|+ \ | ||
| | >-------------------------------||---------------@ BNC
| ___|- / LM386 || 47UF |
| 2 | /| |
| |/|| |
> || v
> 4||7 GND
> ||
| ||
v
GND
To help compensate for the poor low-frequency response of
headphones and small speakers, the headphone amplifier has had a
bass-boost circuit added to it which adds about 6dB to the output
level, centered at 100Hz, dropping to a 0dB boost at 1KHz.
The power level present at the headphones is dependent on the
level in theinput signal and the output impedance. If the input
(digital) value is assumed to be a 16-bit value scaled between +/-1,
then power level on theheadphones is:
Vout = 3*IN
The output is AC coupled by a 47uF capacitor. This means that
there is a roll-off in the frequency response at low frequencies. The
cut-off point canbe approximated as:
Where XH is the impedance of the headphones. For example, with
32ohm headphones the cut-off is at 105Hz. Note that the headphone
output is a voltage. While the output is somewhat higher than normal
line levels, output attenuation in the Codec can reduce his without
loss of dynamic range. At the normal "llne" impedance of
600ohm, the cut-off frequency will be lower; other internal limits
keep the system to a cut-off of about 30Hz.
Internal Loudspeaker
Copyright © Robert Schaffner (support@doitarchive.de) Letzte Aktualisierung am 23. Dezember 2003 |
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