

                       Falcon-A DMA ASIC Description

     This chip provides three channels of DMA for the Atari Falcon
Computer. The ACSI DMA channel from the ST product line is fully
contained and has been modified slightly to accommodate a 5380 SCSI
controller as well as the 1772 FDC. A record and playback DMA
channel for digital sound data are also contained in this chip. The
playback channel is compatible with the existing eight bit stereo
and mono modes from the STE and TT products and has sixteen bit
stereo added.


Pin List

================================================================================
        !            #             !              #              !
  CHIP  !   SIGNAL   #  PGA BOND   ! PGA PACKAGE  #   QFP BOND   ! QFP PACKAGE
  PAD   !    NAME    #    POST     !     PIN      #     POST     !    PIN
 NUMBER !            #   NUMBER    !    NUMBER    #    NUMBER    !   NUMBER
        !            #             !              #              !
================================================================================
    1   !   N/C1     #       1     !      D4      #        1     !      1
--------------------------------------------------------------------------------
    2   !   N/C2     #       2     !      D3      #        2     !      2
--------------------------------------------------------------------------------
    3   !   N/C3     #       3     !      C2      #        3     !      3
--------------------------------------------------------------------------------
    4   !   A31      #       4     !      A1      #        4     !      4
--------------------------------------------------------------------------------
    5   !   A30      #       5     !      D2      #        5     !      5
--------------------------------------------------------------------------------
    6   !   A29      #       6     !      E4      #        6     !      6
--------------------------------------------------------------------------------
    7   !   VDDI1    #       7     !      E3      #        7     !      7
--------------------------------------------------------------------------------
    8   !   VSSI1    #       8     !      B1      #        8     !      8
--------------------------------------------------------------------------------
    9   !   A28      #       9     !      C1      #        9     !      9
--------------------------------------------------------------------------------
   10   !   A27      #      10     !      E2      #       10     !     10
--------------------------------------------------------------------------------
   11   !   A26      #      11     !      F4      #       11     !     11
--------------------------------------------------------------------------------
   12   !   A25      #      12     !      F3      #       12     !     12
--------------------------------------------------------------------------------
   13   !   A24      #      13     !      D1      #       13     !     13
--------------------------------------------------------------------------------
   14   !   A23      #      14     !      F2      #       14     !     14
--------------------------------------------------------------------------------
   15   !   VDDI2    #      15     !      E1      #       15     !     15
--------------------------------------------------------------------------------
   16   !   VSSI2    #      16     !      G4      #       16     !     16
--------------------------------------------------------------------------------
   17   !   A22      #      17     !      G3      #       17     !     17
--------------------------------------------------------------------------------
   18   !   A21      #      18     !      F1      #       18     !     18
--------------------------------------------------------------------------------
   19   !   A20      #      19     !      G2      #       19     !     19
--------------------------------------------------------------------------------
   20   !   A19      #      20     !      G1      #       20     !     20
--------------------------------------------------------------------------------
   21   !   A18      #      21     !      H4      #       21     !     21
--------------------------------------------------------------------------------
   22   !   A17      #      22     !      H3      #       22     !     22
--------------------------------------------------------------------------------
   23   !   VDDI3    #      23     !      H2      #       23     !     23
--------------------------------------------------------------------------------
================================================================================
        !            #             !              #              !
  CHIP  !   SIGNAL   #  PGA BOND   ! PGA PACKAGE  #   QFP BOND   ! QFP PACKAGE
  PAD   !    NAME    #    POST     !     PIN      #     POST     !    PIN
 NUMBER !            #   NUMBER    !    NUMBER    #    NUMBER    !   NUMBER
        !            #             !              #              !
================================================================================
   24   !   VSSI3    #      24     !      H1      #       24     !     24
--------------------------------------------------------------------------------
   25   !   A16      #      25     !      J2      #       25     !     25
--------------------------------------------------------------------------------
   26   !   A15      #      26     !      J4      #       26     !     26
--------------------------------------------------------------------------------
   27   !   A14      #      27     !      J3      #       27     !     27
--------------------------------------------------------------------------------
   28   !   A13      #      28     !      J1      #       28     !     28
--------------------------------------------------------------------------------
   29   !   A12      #      29     !      K1      #       29     !     29
--------------------------------------------------------------------------------
   30   !   A11      #      30     !      K2      #       30     !     30
--------------------------------------------------------------------------------
   31   !   VDDI4    #      31     !      K4      #       31     !     31
--------------------------------------------------------------------------------
   32   !   VSSI4    #      32     !      K3      #       32     !     32
--------------------------------------------------------------------------------
   33   !   A10      #      33     !      L1      #       33     !     33
--------------------------------------------------------------------------------
   34   !   A9       #      34     !      L2      #       34     !     34
--------------------------------------------------------------------------------
   35   !   A8       #      35     !      M1      #       35     !     35
--------------------------------------------------------------------------------
   36   !   A7       #      36     !      L3      #       36     !     36
--------------------------------------------------------------------------------
   37   !   A6       #      37     !      L4      #       37     !     37
--------------------------------------------------------------------------------
   38   !   A5       #      38     !      N1      #       38     !     38
--------------------------------------------------------------------------------
   39   !   VDDI5    #      39     !      M2      #       39     !     39
--------------------------------------------------------------------------------
   40   !   VSSI5    #      40     !      P1      #       40     !     40
--------------------------------------------------------------------------------
   41   !   A4       #      41     !      M3      #       41     !     41
--------------------------------------------------------------------------------
   42   !   A3       #      42     !      M4      #       42     !     42
--------------------------------------------------------------------------------
   43   !   A2       #      43     !      Q1      #       43     !     43
--------------------------------------------------------------------------------
   44   !   A1       #      44     !      N2      #       44     !     44
--------------------------------------------------------------------------------
   45   !   A0       #      45     !      R1      #       45     !     45
--------------------------------------------------------------------------------
   46   !   VDDI6    #      46     !      N3      #       46     !     46
--------------------------------------------------------------------------------
   47   !   VSSI6    #      47     !      P2      #       47     !     47
--------------------------------------------------------------------------------
   48   !   SIZ1     #      48     !      N4      #       48     !     48
--------------------------------------------------------------------------------
   49   !   SIZ0     #      49     !      Q2      #       49     !     49
--------------------------------------------------------------------------------
   50   !   N/C4     #      50     !      P3      #       50     !     50
--------------------------------------------------------------------------------
================================================================================
        !            #             !              #              !
  CHIP  !   SIGNAL   #  PGA BOND   ! PGA PACKAGE  #   QFP BOND   ! QFP PACKAGE
  PAD   !    NAME    #    POST     !     PIN      #     POST     !    PIN
 NUMBER !            #   NUMBER    !    NUMBER    #    NUMBER    !   NUMBER
        !            #             !              #              !
================================================================================
   51   !   N/C5     #      51     !      R2      #       51     !     51
--------------------------------------------------------------------------------
   52   !   N/C6     #      52     !      Q3      #       52     !     52
--------------------------------------------------------------------------------
   53   !   N/C7     #      53     !      P4      #       53     !     53
--------------------------------------------------------------------------------
   54   !   N/C8     #      54     !      Q4      #       54     !     54
--------------------------------------------------------------------------------
   55   !   N/C9     #      55     !      R3      #       55     !     55
--------------------------------------------------------------------------------
   56   !   N/C10    #      56     !      S1      #       56     !     56
--------------------------------------------------------------------------------
   57   !   TM2      #      57     !      R4      #       57     !     57
--------------------------------------------------------------------------------
   58   !   TM1      #      58     !      P5      #       58     !     58
--------------------------------------------------------------------------------
   59   !   TM0      #      59     !      Q5      #       59     !     59
--------------------------------------------------------------------------------
   60   !   VDDI7    #      60     !      S2      #       60     !     60
--------------------------------------------------------------------------------
   61   !   VSSI7    #      61     !      S3      #       61     !     61
--------------------------------------------------------------------------------
   62   !   TT1      #      62     !      R5      #       62     !     62
--------------------------------------------------------------------------------
   63   !   TT0      #      63     !      P6      #       63     !     63
--------------------------------------------------------------------------------
   64   !   ST0*     #      64     !      Q6      #       64     !     64
--------------------------------------------------------------------------------
   65   !   ST1*     #      65     !      S4      #       65     !     65
--------------------------------------------------------------------------------
   66   !   BCLK     #      66     !      R6      #       66     !     66
--------------------------------------------------------------------------------
   67   !   TA1*     #      67     !      S5      #       67     !     67
--------------------------------------------------------------------------------
   68   !   TA0*     #      68     !      P7      #       68     !     68
--------------------------------------------------------------------------------
   69   !   VDDI8    #      69     !      Q7      #       69     !     69
--------------------------------------------------------------------------------
   70   !   VSSI8    #      70     !      S6      #       70     !     70
--------------------------------------------------------------------------------
   71   !   RXW      #      71     !      R7      #       71     !     71
--------------------------------------------------------------------------------
   72   !   BR*      #      72     !      S7      #       72     !     72
--------------------------------------------------------------------------------
   73   !   BGO*     #      73     !      P8      #       73     !     73
--------------------------------------------------------------------------------
   74   !   BGI*     #      74     !      Q8      #       74     !     74
--------------------------------------------------------------------------------
   75   !   RESET*   #      75     !      R8      #       75     !     75
--------------------------------------------------------------------------------
   76   !   TE*      #      76     !      S8      #       76     !     76
--------------------------------------------------------------------------------
   77   !   VDDC1    #      77     !      R9      #       77     !     77
--------------------------------------------------------------------------------
================================================================================
        !            #             !              #              !
  CHIP  !   SIGNAL   #  PGA BOND   ! PGA PACKAGE  #   QFP BOND   ! QFP PACKAGE
  PAD   !    NAME    #    POST     !     PIN      #     POST     !    PIN
 NUMBER !            #   NUMBER    !    NUMBER    #    NUMBER    !   NUMBER
        !            #             !              #              !
================================================================================
   78   !   VSSC1    #      78     !      P9      #       78     !     78
--------------------------------------------------------------------------------
   79   !   PSGIN    #      79     !      Q9      #       79     !     79
--------------------------------------------------------------------------------
   80   !   CDDIN    #      80     !      S9      #       80     !     80
--------------------------------------------------------------------------------
   81   !   EXTCLK   #      81     !     S10      #       81     !     81
--------------------------------------------------------------------------------
   82   !   CLK25I   #      82     !     R10      #       82     !     82
--------------------------------------------------------------------------------
   83   !   BA*      #      83     !     P10      #       83     !     83
--------------------------------------------------------------------------------
   84   !   BMODE    #      84     !     Q10      #       84     !     84
--------------------------------------------------------------------------------
   85   !   PLYCLK   #      85     !     S11      #       85     !     85
--------------------------------------------------------------------------------
   86   !   VDDI9    #      86     !     R11      #       86     !     86
--------------------------------------------------------------------------------
   87   !   VSSI9    #      87     !     S12      #       87     !     87
--------------------------------------------------------------------------------
   88   !   PLYSYNC  #      88     !     Q11      #       88     !     88
--------------------------------------------------------------------------------
   89   !   PLYDATA  #      89     !     P11      #       89     !     89
--------------------------------------------------------------------------------
   90   !   RECCLK   #      90     !     S13      #       90     !     90
--------------------------------------------------------------------------------
   91   !   RECSYNC  #      91     !     R12      #       91     !     91
--------------------------------------------------------------------------------
   92   !   CDDOUT   #      92     !     S14      #       92     !     92
--------------------------------------------------------------------------------
   93   !   CDSYNC   #      93     !     Q12      #       93     !     93
--------------------------------------------------------------------------------
   94   !   VDDI10   #      94     !     P12      #       94     !     94
--------------------------------------------------------------------------------
   95   !   VSSI10   #      95     !     S15      #       95     !     95
--------------------------------------------------------------------------------
   96   !   CDCLK    #      96     !     R13      #       96     !     96
--------------------------------------------------------------------------------
   97   !   SCLOCK   #      97     !     S16      #       97     !     97
--------------------------------------------------------------------------------
   98   !   SC0      #      98     !     Q13      #       98     !     98
--------------------------------------------------------------------------------
   99   !   SCLK     #      99     !     R14      #       99     !     99
--------------------------------------------------------------------------------
  100   !   RECDATA  #     100     !     P13      #      100     !    100
--------------------------------------------------------------------------------
  101   !   STD      #     101     !     R15      #      101     !    101
--------------------------------------------------------------------------------
  102   !   N/C11    #     102     !     Q14      #      102     !    102
--------------------------------------------------------------------------------
  103   !   N/C12    #     103     !     R16      #      103     !    103
--------------------------------------------------------------------------------
  104   !   N/C13    #     104     !     Q15      #      104     !    104
--------------------------------------------------------------------------------
================================================================================
        !            #             !              #              !
  CHIP  !   SIGNAL   #  PGA BOND   ! PGA PACKAGE  #   QFP BOND   ! QFP PACKAGE
  PAD   !    NAME    #    POST     !     PIN      #     POST     !    PIN
 NUMBER !            #   NUMBER    !    NUMBER    #    NUMBER    !   NUMBER
        !            #             !              #              !
================================================================================
  105   !   N/C14    #     105     !     P14      #      105     !    105
--------------------------------------------------------------------------------
  106   !   N/C15    #     106     !     P15      #      106     !    106
--------------------------------------------------------------------------------
  107   !   HDINT    #     107     !     Q16      #      107     !    107
--------------------------------------------------------------------------------
  108   !   SINT     #     108     !     S17      #      108     !    108
--------------------------------------------------------------------------------
  109   !   SCNT     #     109     !     P16      #      109     !    109
--------------------------------------------------------------------------------
  110   !   SC1      #     110     !     N14      #      110     !    110
--------------------------------------------------------------------------------
  111   !   SC2      #     111     !     N15      #      111     !    111
--------------------------------------------------------------------------------
  112   !   VDDI11   #     112     !     R17      #      112     !    112
--------------------------------------------------------------------------------
  113   !   VSSI11   #     113     !     Q17      #      113     !    113
--------------------------------------------------------------------------------
  114   !   CLK25O   #     114     !     N16      #      114     !    114
--------------------------------------------------------------------------------
  115   !   FCS*     #     115     !     M14      #      115     !    115
--------------------------------------------------------------------------------
  116   !   DSKIRQ*  #     116     !     M15      #      116     !    116
--------------------------------------------------------------------------------
  117   !   FDINT    #     117     !     P17      #      117     !    117
--------------------------------------------------------------------------------
  118   !   SRD      #     118     !     M16      #      118     !    118
--------------------------------------------------------------------------------
  119   !   CD0      #     119     !     N17      #      119     !    119
--------------------------------------------------------------------------------
  120   !   CD1      #     120     !     L14      #      120     !    120
--------------------------------------------------------------------------------
  121   !   VDDI12   #     121     !     L15      #      121     !    121
--------------------------------------------------------------------------------
  122   !   VSSI12   #     122     !     M17      #      122     !    122
--------------------------------------------------------------------------------
  123   !   CD2      #     123     !     L16      #      123     !    123
--------------------------------------------------------------------------------
  124   !   CD3      #     124     !     L17      #      124     !    124
--------------------------------------------------------------------------------
  125   !   CD4      #     125     !     K14      #      125     !    125
--------------------------------------------------------------------------------
  126   !   CD5      #     126     !     K15      #      126     !    126
--------------------------------------------------------------------------------
  127   !   CD6      #     127     !     K16      #      127     !    127
--------------------------------------------------------------------------------
  128   !   CD7      #     128     !     K17      #      128     !    128
--------------------------------------------------------------------------------
  129   !   VDDI13   #     129     !     J16      #      129     !    129
--------------------------------------------------------------------------------
  130   !   VSSI13   #     130     !     J14      #      130     !    130
--------------------------------------------------------------------------------
  131   !   CA0      #     131     !     J15      #      131     !    131
--------------------------------------------------------------------------------
================================================================================
        !            #             !              #              !
  CHIP  !   SIGNAL   #  PGA BOND   ! PGA PACKAGE  #   QFP BOND   ! QFP PACKAGE
  PAD   !    NAME    #    POST     !     PIN      #     POST     !    PIN
 NUMBER !            #   NUMBER    !    NUMBER    #    NUMBER    !   NUMBER
        !            #             !              #              !
================================================================================
  132   !   CA1      #     132     !     J17      #      132     !    132
--------------------------------------------------------------------------------
  133   !   CA2      #     133     !     H17      #      133     !    133
--------------------------------------------------------------------------------
  134   !   CRW      #     134     !     H16      #      134     !    134
--------------------------------------------------------------------------------
  135   !   FRQ      #     135     !     H14      #      135     !    135
--------------------------------------------------------------------------------
  136   !   CLK32    #     136     !     H15      #      136     !    136
--------------------------------------------------------------------------------
  137   !   VDDC2    #     137     !     G17      #      137     !    137
--------------------------------------------------------------------------------
  138   !   VSSC2    #     138     !     G16      #      138     !    138
--------------------------------------------------------------------------------
  139   !   DISKCHNG #     139     !     F17      #      139     !    139
--------------------------------------------------------------------------------
  140   !   MDET1    #     140     !     G15      #      140     !    140
--------------------------------------------------------------------------------
  141   !   MDET2    #     141     !     G14      #      141     !    141
--------------------------------------------------------------------------------
  142   !   MODE1    #     142     !     E17      #      142     !    142
--------------------------------------------------------------------------------
  143   !   MODE2    #     143     !     F16      #      143     !    143
--------------------------------------------------------------------------------
  144   !   CLK8     #     144     !     D17      #      144     !    144
--------------------------------------------------------------------------------
  145   !   FCCLK    #     145     !     F15      #      145     !    145
--------------------------------------------------------------------------------
  146   !   VDDI14   #     146     !     F14      #      146     !    146
--------------------------------------------------------------------------------
  147   !   VSSI14   #     147     !     C17      #      147     !    147
--------------------------------------------------------------------------------
  148   !   GPIO0    #     148     !     E16      #      148     !    148
--------------------------------------------------------------------------------
  149   !   GPIO1    #     149     !     B17      #      149     !    149
--------------------------------------------------------------------------------
  150   !   GPIO2    #     150     !     E15      #      150     !    150
--------------------------------------------------------------------------------
  151   !   ACK*     #     151     !     D16      #      151     !    151
--------------------------------------------------------------------------------
  152   !   HCS*     #     152     !     E14      #      152     !    152
--------------------------------------------------------------------------------
  153   !   HRQ      #     153     !     C16      #      153     !    153
--------------------------------------------------------------------------------
  154   !   TEST     #     154     !     D15      #      154     !    154
--------------------------------------------------------------------------------
  155   !   N/C16    #     155     !     B16      #      155     !    155
--------------------------------------------------------------------------------
  156   !   N/C17    #     156     !     C15      #      156     !    156
--------------------------------------------------------------------------------
  157   !   N/C18    #     157     !     D14      #      157     !    157 
--------------------------------------------------------------------------------
  158   !   N/C19    #     158     !     C14      #      158     !    158
--------------------------------------------------------------------------------
================================================================================
        !            #             !              #              !
  CHIP  !   SIGNAL   #  PGA BOND   ! PGA PACKAGE  #   QFP BOND   ! QFP PACKAGE
  PAD   !    NAME    #    POST     !     PIN      #     POST     !    PIN
 NUMBER !            #   NUMBER    !    NUMBER    #    NUMBER    !   NUMBER
        !            #             !              #              !
================================================================================
  159   !   N/C20    #     159     !     B15      #      159     !    159
--------------------------------------------------------------------------------
  160   !   D31      #     160     !     A17      #      160     !    160
--------------------------------------------------------------------------------
  161   !   D30      #     161     !     B14      #      161     !    161
--------------------------------------------------------------------------------
  162   !   D29      #     162     !     D13      #      162     !    162
--------------------------------------------------------------------------------
  163   !   D28      #     163     !     C13      #      163     !    163
--------------------------------------------------------------------------------
  164   !   VDDI15   #     164     !     A16      #      164     !    164
--------------------------------------------------------------------------------
  165   !   VSSI15   #     165     !     A15      #      165     !    165
--------------------------------------------------------------------------------
  166   !   D27      #     166     !     B13      #      166     !    166
--------------------------------------------------------------------------------
  167   !   D26      #     167     !     D12      #      167     !    167
--------------------------------------------------------------------------------
  168   !   D25      #     168     !     C12      #      168     !    168
--------------------------------------------------------------------------------
  169   !   D24      #     169     !     A14      #      169     !    169
--------------------------------------------------------------------------------
  170   !   D23      #     170     !     B12      #      170     !    170
--------------------------------------------------------------------------------
  171   !   D22      #     171     !     A13      #      171     !    171
--------------------------------------------------------------------------------
  172   !   VDDI16   #     172     !     D11      #      172     !    172
--------------------------------------------------------------------------------
  173   !   VSSI16   #     173     !     C11      #      173     !    173
--------------------------------------------------------------------------------
  174   !   D21      #     174     !     A12      #      174     !    174
--------------------------------------------------------------------------------
  175   !   D20      #     175     !     B11      #      175     !    175
--------------------------------------------------------------------------------
  176   !   D19      #     176     !     A11      #      176     !    176
--------------------------------------------------------------------------------
  177   !   VDDC3    #     177     !     D10      #      177     !    177
--------------------------------------------------------------------------------
  178   !   VSSC3    #     178     !     C10      #      178     !    178
--------------------------------------------------------------------------------
  179   !   D18      #     179     !     B10      #      179     !    179
--------------------------------------------------------------------------------
  180   !   D17      #     180     !     A10      #      180     !    180
--------------------------------------------------------------------------------
  181   !   D16      #     181     !      B9      #      181     !    181
--------------------------------------------------------------------------------
  182   !   VDDI17   #     182     !      D9      #      182     !    182
--------------------------------------------------------------------------------
  183   !   VSSI17   #     183     !      C9      #      183     !    183
--------------------------------------------------------------------------------
  184   !   D15      #     184     !      A9      #      184     !    184
--------------------------------------------------------------------------------
  185   !   D14      #     185     !      A8      #      185     !    185
--------------------------------------------------------------------------------
================================================================================
        !            #             !              #              !
  CHIP  !   SIGNAL   #  PGA BOND   ! PGA PACKAGE  #   QFP BOND   ! QFP PACKAGE
  PAD   !    NAME    #    POST     !     PIN      #     POST     !    PIN
 NUMBER !            #   NUMBER    !    NUMBER    #    NUMBER    !   NUMBER
        !            #             !              #              !
================================================================================
  186   !   D13      #     186     !      B8      #      186     !    186
--------------------------------------------------------------------------------
  187   !   D12      #     187     !      D8      #      187     !    187
--------------------------------------------------------------------------------
  188   !   D11      #     188     !      C8      #      188     !    188
--------------------------------------------------------------------------------
  189   !   D10      #     189     !      A7      #      189     !    189
--------------------------------------------------------------------------------
  190   !   VDDI18   #     190     !      B7      #      190     !    190
--------------------------------------------------------------------------------
  191   !   VSSI18   #     191     !      A6      #      191     !    191
--------------------------------------------------------------------------------
  192   !   D9       #     192     !      C7      #      192     !    192
--------------------------------------------------------------------------------
  193   !   D8       #     193     !      D7      #      193     !    193
--------------------------------------------------------------------------------
  194   !   D7       #     194     !      A5      #      194     !    194
--------------------------------------------------------------------------------
  195   !   D6       #     195     !      B6      #      195     !    195
--------------------------------------------------------------------------------
  196   !   D5       #     196     !      A4      #      196     !    196       
--------------------------------------------------------------------------------
  197   !   D4       #     197     !      C6      #      197     !    197       
--------------------------------------------------------------------------------
  198   !   VDDI19   #     198     !      D6      #      198     !    198       
--------------------------------------------------------------------------------
  199   !   VSSI19   #     199     !      A3      #      199     !    199       
--------------------------------------------------------------------------------
  200   !   D3       #     200     !      B5      #      200     !    200       
--------------------------------------------------------------------------------
  201   !   D2       #     201     !      A2      #      201     !    201       
--------------------------------------------------------------------------------
  202   !   D1       #     202     !      C5      #      202     !    202       
--------------------------------------------------------------------------------
  203   !   D0       #     203     !      B4      #      203     !    203       
--------------------------------------------------------------------------------
  204   !   N/C21    #     204     !      D5      #      204     !    204       
--------------------------------------------------------------------------------
  205   !   N/C22    #     205     !      B3      #      205     !    205       
--------------------------------------------------------------------------------
  206   !   N/C23    #     206     !      C4      #      206     !    206       
--------------------------------------------------------------------------------
  207   !   N/C24    #     207     !      B2      #      207     !    207       
--------------------------------------------------------------------------------
  208   !   N/C25    #     208     !      C3      #      208     !    208       
--------------------------------------------------------------------------------

Pin Description

TM0-TM2   BiDir     Fbus function code. These lines are normally
                    inputs. They become outputs during DMA when
                    the Fbus is granted. Only values of 5 and 6
                    (supervisor program and data) will allow IO
                    access. A value of 5 is output during DMA.

A0-A31    BiDir     Fbus address. These lines are normally inputs.
                    They become outputs during DMA when the Fbus
                    is granted. They are used to select registers
                    during IO and to address memory during DMA.

D0-D31    BiDir     Fbus data. These lines are inputs for IO
                    writes and DMA reads and outputs for IO reads
                    and DMA writes. They are used for data
                    transfer between the chip and the Fbus.

BCLK      Input     Falcon Bus clock.

BMODE     BiDir     Fbus mode select line. It is input during IO
                    to indicate the current Fbus mode. It is
                    driven low during DMA.

ST0_-ST1  BiDir     Fbus strobes. These lines are inputs during IO
                    and outputs during DMA. They are used to
                    qualify the Fbus cycle.

SIZ0-SIZ1 BiDir     Fbus size select lines. These lines are input
                    during IO and an output during DMA. They are
                    used to qualify the active portion of the data
                    bus.

TT0-TT1   BiDir     Fbus transfer type select. These lines is an
                    input during IO and an output during DMA. They
                    are used to qualify the type of Fbus transfer.

R/W       BiDir     Fbus read write. This line is an input during
                    IO and indicates a read of the chip when high
                    and a write to the chip when low. This line is
                    an output during DMA and indicates a read of
                    the bus when high and a write to the bus when
                    low.

TA0_-TA1  BiDir     Fbus transfer acknowledge and transfer burst
                    inhibit. These lines are output during IO and
                    indicate to the Fbus master that the current
                    cycle can be terminated and should be burst
                    inhibited. During DMA these lines are input to
                    determine when to terminate a DMA cycle.

TE_       Input     This signal is used to terminate a DMA cycle
                    when the system detects a bus error. It is
                    provided to prevent system lockup when a bus
                    error occurs during DMA. It is also used by
                    the register decode circuitry to detect a bus
                    error on a faulty 040 mode register access.

BR_       OD output This output is driven low when the Fbus is
                    needed to perform DMA cycles.

BGI_      Input     A low on this input indicates that the Fbus is
                    granted and that the chip can assume control
                    of the bus at the completion of the current
                    cycle, if one is in progress, or immediately.

BGO_      Output    This output is provided to support a daisy
                    chain on the bus grant line to arbitrate
                    multiple bus requests. When the chip is not
                    requesting the bus, this output is driven to
                    match the BGI_ input else it is driven high
                    (inactive).

BA_       TS output This output is driven low when the chip
                    assumes the bus after the request grant
                    handshake. When DMA operations have been
                    completed and the chip releases the bus, this
                    line is driven high then tri-stated.

RESET_    Input     A low on this input resets the chip and clears
                    any current operational mode.

GPIO0-GPIO2 BiDir   These pins are general purpose IO pins which
                    may be programmed as inputs or outputs.

CLK25I    Input     This input is the 25Mhz clock used by the
                    sound logic.

CLK25O    Output    This output is a buffered version of the
                    CLK25I input pin.

EXTCLK    Input     This input is the sound channel external
                    clock.

RECCLK    Output    The clock for the external serial data input.

RECSYNC   BiDir     The sync signal for the external serial data
                    coming into the chip when an output. The
                    handshake control when an input.

RECDATA   Input     This input is the data from the external
                    serial input channel.

PLYCLK    Output    The clock for the external serial data output.

PLYSYNC   BiDir     The sync signal for the external serial data
                    leaving the chip when an output. The handshake
                    control when an input

PLYDATA   Output    This output is the data to the external serial
                    output channel.

SCLOCK    Output    This is the main clock to the CODEC.

CDCLK     Output    This is the serial bit clock to the CODEC.

CDSYNC    Output    The sync for the CODEC serial interface.

CDDOUT    Output    The serial data for the CODEC DAC.

CDDIN     Input     The serial data from the CODEC ADC.

SC0       TS Output The serial clock output to the DSP receive
                    serial channel. The output is enabled by
                    setting bit 7 of the RCV register.

SC1       BiDir     The sync for the DSP receive serial channel.
                    when the output is enabled by setting bit 4 of
                    the RCV register. The handshake control when
                    an input.

SRD       TS Output The serial data output to the DSP receive
                    serial channel. This output is enabled if
                    either bit 7 or bit 4 of the RCV register are
                    set.

SCLK      BiDir     The serial clock output to the DSP transmit
                    serial channel. The output is enabled by
                    setting bit 7 of the SRC register.

SC2       BiDir     The sync for the DSP transmit serial channel.
                    when the output is enabled by setting bit 4 of
                    the SRC register. The handshake control when
                    an input.

STD       Input     The serial data input from the DSP transmit
                    serial channel.


SINT      Output    This output is low when sound DMA is active
                    and high otherwise. It will make a high to low
                    transition at the beginning of a frame of
                    sound data and a low to high transition at the
                    end of the frame. This signal can be
                    programmed to come from either the record or
                    play channels.

SCNT      Output    This output is similar to SINT but is wider.

TEST      Input     When this input is high, the ACSI sector count
                    can be read in the high byte of the ACSI
                    status register. Also a low to high transition
                    on this signal increments the sound DMA
                    address counters and the ACSI sector prescale
                    and count. This pin should be tied low for
                    normal system operation.

DSKIRQ_   OD output FDINT high or HDINT_ low make this output low.

FDINT     Input     This input affects DSKIRQ_ only.

HDINT_    Input     This input affects DSKIRQ_ only.

FRQ       Input     Active high DMA request from the FDC.

FCS_      Output    Active low chip select to the FDC.

HRQ       Input     Active high DMA request from the SCSI
                    controller.

HCS_      Output    Active low chip select to the SCSI controller.

ACK_      Output    Active low DMA acknowledge to the SCSI
                    controller.

CD0-CD7   BiDir     Data bus for the FDC and SCSI controller.

CA0-CA2   Output    Register address to the FDC and SCSI
                    controller. Used to select FDC or SCSI
                    controller registers during IO.

CRW       Output    A high means transfer from the FDC or SCSI
                    controller. A low means transfer to the FDC or
                    SCSI controller.

DISKCHNG  Input     Status input for the floppy density select
                    register.

MODE0-MODE1 Outputs Status outputs for the floppy density select
                    register.

MDET0-MDET1 Inputs  Status inputs for the floppy density select
                    register.

CLK32     Input     The 32 Mhz clock input.

CLK8      Output    Free-running 32 Mhz clock divided by four.

FCCLK     Output    32 Mhz clock divided by 1, 2, or 4 as selected
                    by the floppy density select register.

Hierarchical Map and Description

ADMA      The 12 page schematic ADMA is the highest level of the
          chip. Page 10 contains the address IO buffers. Page 11
          contains the data IO buffers and page 8 the data selector
          (DMUX). Page 7 contains several other IO buffers. Page 6
          is the reference to the address decoder (DECODER). Page
          9 contains the DSP IO buffers. Page 1 contains the bus
          interface circuitry for DMA (BCYLGEN, ARBIT, and
          AOUTMUX). Page 2 is the reference to the ACSI DMA
          channel. Page 12 is the IO buffers for the ACSI channel
          data. Page 3 is the reference to the sound DMA channel.
          Page 4 refers to the sound serial data matrix circuitry.
          Page 5 contains the 32 Mhz clock divider chain, the pulse
          stretcher circuits for SINT and SCNT, and the disk
          interrupt gate.

Decode    The 8 page schematic is the address decoding for the
          chip. This circuit decodes the internal register selects,
          data path, and IO acknowledges.

DMux      This circuit selects from the various internal data
          sources and converts to the 32 bit output data format as
          appropriate.

Arbit     This state machine controls each DMA channels arbitration
          for the Fbus.

BCylGen   This state machine generates the bus control strobes
          during DMA.


AOutMux   This 1 of 3 by 30 selector with imbedded latches is used
          to select the current DMA channels address for output
          during DMA.

ACSIDMA   This collection of circuits form the ACSI DMA channel.

ACSI      These 12 pages of schematic are the ST DMA (ST-4140) chip
          converted to an internal cell.

ThruCntl  This state machine generates IO control for the ACSI
          cell.

DMACntl   This state machine generates DMA control for the ACSI
          cell.

MFifo     A bidirectional FIFO with conversion from 32 bit to 16
          bit data formats.

ADCntr    31 bit counter for address generation during ACSI DMA.

DOutMux   1 of 2 by 16/8 selector for data selection.

RGLH16    16 LH latches.

RGMux16   16 MX21 selectors.

FDSelRg   Floppy density select register. Contains the register and
          circuit for generating FCCLK.

SndChan   Three pages integrate the playback and record sound DMA
          channels. Page 1 contains the part of the sound DMA
          control register which selects the playback or record
          channel source for the SINT and SCNT signals. Pages two
          and three reference the Playback and Record channels.

SDOutMux  Contains buffers to drive otherwise tri-stated data
          lines.

SndTop    31 bit register to hold the address of the top of the
          sound frame.

SndComp   31 bit comparitor to detect when the sound address equals
          the top of the frame.

SndCntr   31 bit counter to hold the sound address.

SndBase   31 bit register to hold the base address of the sound
          frame.

PlayMReg  Play mode register.

PlyTGen   Timing control circuitry for the serial output.

PFifo     A 16 word FIFO for playback data. Has a 32 bit input and
          16 bit output.

RFifo     A 16 word FIFO for record data. Has a 16 bit input and 32
          bit output.

SndSteer  A circuit to convert the data from 8 bit stereo or mono
          to 16 bit stereo for output.

SDOut     A shift register to serialize play data for output.

SDIn      A shift register to receive the serial record data.

PlayCntl  A small circuit to interface the ARBIT logic to the
          playback channel.

RecCntl   A small circuit to interface the ARBIT logic to the
          record channel.

RecTGen   Timing control circuitry for the serial input.

Matrix    This collection of circuits form a 4x4 matrix to route
          the sound serial data through the chip.

MtrxRegs  The registers controlling the matrix.

ClkMatrx  The portion of the matrix routing the various serial
          clocks.

AClkSw    A synchronous clock selector.

FramGen   This circuit derives the various sub clocks from the
          selected master clock.

Fram32    A subset of FRAMGEN for the 32Mhz clock.

CODECMux  The portion of the matrix dealing with the CODEC
          interface.

Reg8      A eight bit register.

Reg4      A four bit register.

GCkGen    A circuit for gating the clock as controlled by
          handshake.

Cnt3Rpl   A three bit ripple counter.

Cnt4Rpl   A four bit ripple counter.



Registers


The following registers are contained with the chip:





xxFF8604 - ACSI DMA Data Register WDC (RW)


D15                D8
D7D0


XX
write only sector counter (14 bits)


XXXXXXXX
IO data (8 bits)


The ACSI DMA data register (WDC) is described in the ACSI
Integration Guide.





xxFF8606 - ACSI Mode Register WDL (WO)


 D15                  D8 
 D7D0 


0000000
dir
src
r
ff
scs
ts
ad


     dir - ACSI DMA direction (0=into mem)
     src - ACSI DMA source (0=SCSI, 1=floppy)
     r   - reserved
     ff  - fifo flush (1 causes fifo flush operation)
     scs - sector counter select (1 enables sector counter access)
     ts  - IO target select (0=FDC, 1=SCSI)
     ad  - IO register select (3 bits, CA2-CA0)

The ACSI mode register (WDL) is described in the ACSI Integration
Guide. New to the SDMA is the addition of a register select bit 0
(CA0). This bit is used as the LSB of the register address when
accessing the SCSI controller. It has no effect on accesses to the
floppy controller.




xxFF8606 - ACSI Status Register (RO)


 D15                    D8 
 D7D0 


00000000000
f
d
r
z
e


     f  - Fifo status (0 = ACSI fifos empty)
     d  - State of DIR bit in ACSI mode register
     r  - DMA request (1 if selected port requesting)
     z  - low if sector counter is zero
     e  - ERROR, low if ACSI data overrun or underrun

Bits 0-2 are referenced in the ACSI Integration Guide. Bit 3 has
existed in previous designs but has never been documented (nor is
very useful). Bit 4, fifo status, is intended to facilitate use of
the ACSI fifo flush function.

Note:     The ACSI registers must be accessed as words even though
          less than 16 bits are defined for the registers.


xxFF8601  rw   ACSI base addr upper-upper byte
xxFF8609  rw   ACSI base addr upper-middle byte
xxFF860B  rw   ACSI base addr lower-middle byte
xxFF860D  rw   ACSI base addr lower-lower (7 bits, bit 0 fixed)

Note:     The ACSI base address registers exist on the odd bytes
          only.





xxFF860F - Floppy Density Select Register (RW)  


 D15        D8 
D7D0


00000000
dc
mt2
md2
fs1
sta
mt1
md1
fs0


     dc  - DISKCHNG input pin state (read only)
     mt2 - MDET2 input pin state (read only)
     md2 - MODE2 output pin state
     sta - Internal DMA status (read only)1
     mt1 - MDET1 input pin state (read only)
     md1 - MODE1 output pin state
     fs  - FCCLK frequency select
          00 - 8Mhz (default)
          01 - 16 Mhz
          10 - 32 Mhz
          11 - off

Note 1:   This bit was added to the SDMA to help avoid a problem
          created by the decoupling of the bus and ACSI peripheral
          timing. Accessing the WDC or WDL registers when the ACSI
          DMA channel is active can potentially lock up the system.
          Software should poll the status bit before any access to
          either the WDC or WDL registers. If the bit reads high,
          continue polling until it reads low. This is intended
          primarily for the case where an ACSI DMA write has been
          initiated by setting the sector count and the peripheral
          must be instructed to begin the transfer by sending a
          command via the WDL and WDC registers. Polling the status
          bit will insure that the command transfer happens after
          the fifo fill DMA operation has completed. Software
          should otherwise avoid accesses to WDC or WDL anytime the
          sector count is believed to be non-zero.





xxFF8900 - Sound DMA Control Register (RW)


 D15              D8 
 D7D0 


0000
sc
si
rs
0
rf
re
00
pf
pe


     si - SINT source select
          00 - SINT high
          01 - play (default)
          10 - record
          11 - play OR record

     sc - SCNT source select
          00 - SCNT high
          01 - play (default)
          10 - record
          11 - play OR record

     rs - register set select (0=playback register set)

     rf - record frame repeat (0=single frame)
     re - record DMA enable (1=on)

     pf - playback frame repeat (0=single frame)
     pe - playback DMA enable (1=on)

Sound DMA address pointers:

xxFF8915  rw   Sound frame base addr upper-upper byte
xxFF8903  rw   Sound frame base addr upper-middle byte
xxFF8905  rw   Sound frame base addr lower-middle byte
xxFF8907  rw   Sound frame base addr lower-lower (7 bits)

xxFF8917  rw   Sound frame addr upper-upper byte
xxFF8909  rw   Sound frame addr upper-middle byte
xxFF890B  rw   Sound frame addr lower-middle byte
xxFF890D  rw   Sound frame addr lower-lower (7 bits)

xxFF8919  rw   Sound frame top addr upper-upper byte
xxFF890F  rw   Sound frame top addr upper-middle byte
xxFF8911  rw   Sound frame top addr lower-middle byte
xxFF8913  rw   Sound frame top addr lower-lower (7 bits)

Note:     The sound frame address registers exist on the odd bytes
          only.






xxFF8920 Playback Mode Control Register (RW)


D15              D8
D7D0


00
pms
00
pts
md
0000
pc


     pms - Playback monitor select
          00 - tracks 1 & 2
          01 - tracks 3 & 4
          10 - tracks 5 & 6
          11 - tracks 7 & 8
          
     pts - Playback track select
          00 - 2 tracks
          01 - 4 tracks
          10 - 6 tracks
          11 - 8 tracks

     md - play mode
          00 - 8 bit stereo
          10 - 8 bit mono
          X1 - 16 bit stereo

     pc - sample rate prescaler select1
          00 - /1280
          01 - /640
          10 - /320
          11 - /160

FF8922    rw   MicroWire data register2
FF8924    rw   MicroWire mask register

Note 1:   Only effective if the internal clock prescaler is off.
          (xxFF8935 - D0-D3=0000)

Note 2:   The Microwire registers are dummy registers existing for
          compatibility only and must be accessed as words.




     xxFF8930 Data Path and Clock Matrix Source: SRC (RW)


D15 D8
D7D0


CODEC xmit1
Ext. transmit
DSP transmit
Playback


00b0
0abhe
dabhd
sabg



     ab - Clock Selector
          00 - 25.175MHz
          01 - External
          10 - 32MHz
          11 - Reserved

     d  - DSP Transmit Clock Direction2
          1  - The DSP transmit clock (SCLK) is output.


     he  - Sync direction (RECSYNC)3
          1  - Output enabled

     hd  - Sync direction (SC2)3
          1  - Output enabled

     g  - Gated clock (handshake) disable4
          1  - continuous clock mode

     s  - Source for Handshake Control4
          0  - DSP Receive
          1  - External Output

Note 1:   The CODEC may only select the 25.175Mhz or external
          clocks.

Note 2:   SCLK should normally be configured as an output. This bit
          is provided to be used in conjunction with bit 4 to
          disable both the clock and sync outputs when the DSP SSI
          port is controlled exclusively by an external source.

Note 3:   These bits should only be set to 0 if the corresponding
          port is directed via the matrix to the record DMA channel
          and the record DMA channel is configured for gated clock
          mode. Bit 4 (hd) can also be set to zero for the
          condition outlined in note 2 above. Otherwise these bits
          should be set to 1.

Note 4:   When bit 0 (g)is set to 0, the clock to the receiving
          port is gated off when no data is available, when the
          sync signal from the port selected by bit 3 (s) is low,
          or when the DMA channel is not active. The selected port
          sync signal should be configured as an input in this
          case. When this bit is set to a 1, the receiving port is
          sent a continuous clock.




          FF8932 DATA and Clock Matrix :Receive (RW) 


D15     D8
D7D0


CODEC rcv.
Ext. receive
DSP receive
Record


0ab0
0abhe
dabhd
sabg



     ab - Source Device Data and Clock
          00 - DMA Out (Playback)
          01 - DSP Transmit
          10 - External Input
          11 - ADC

     d  - DSP Receive Clock Direction1
          1  - The DSP receive clock (SC0) is output.

     he  - Sync direction (PLYSYNC)2
          1  - Output enabled

     hd  - Sync direction (SC1)2
          1  - Output enabled

     g  - Gated clock (handshake) disable3
          1  - continuous clock mode

     s  - Source For Handshake Control3
          0  - DSP Transmit
          1  - External Input

Note 1:   SC0 should normally be configured as an output. This bit
          is provided to be used in conjuction with bit 4 to
          disable both the clock and sync outputs when the DSP SSI
          port is controlled exclusively by an external source.

Note 2:   These bits should only be set to 0 if the corresponding
          port is receiving via the matrix from the playback DMA
          channel and the playback DMA channel is configured for
          gated clock mode. Bit 4 (hd) can also be set to zero for
          the condition outlined in note 1 above. Otherwise these
          bits should be set to 1.

Note 3:   When bit 0 (g)is set to 0, the clock to the transmitting
          port is gated off when the input FIFO is full, when the
          sync signal from the port selected by bit 3 (s) is low,
          or when the DMA channel is not active. The selected port
          sync signal should be configured as an input in this
          case. When this bit is set to a 1, the transmitting port
          is sent a continuous clock.





    FF8934 Prescaler for Internal and External Clocks (RW)


D15D8
D7D0


External Clock
Internal Clock


 0000
dddd
0000
dddd


     dddd - Prescaler for  Internal and External Clocks

          0000 - off1
          0001 - Divide by 2
           .
          1011 - Divide by 12

Note 1:   When the internal clock is prescale value is set to 0000,
          the prescale value selected by bits 0 and 1 of the
          Playback Mode Control Register (xxFF8920) will take
          effect.




              FF8936 DAC and Record Control (RW)


D15          D8
D7D0


000000
rr
0000
r
p
e
a



     rr - Record Channel Select
          00 - Record tracks 1 and 2
          01 - Record tracks 1 thru 4
          10 - Record tracks 1 thru 6
          11 - Record tracks 1 thru 8 ( ie. all )

     r  - Global Sound Reset
          1  - Reset Sound Subsection
               ( Not self clearing )

     p  - Input Select1
          0  - CODEC ADC
          1  - PSG

     e  - Matrix output to CODEC enable2
          1  - Enable matrix data output to the CODEC

     a  - Alternate data output to CODEC enable1,2
          1  - Enable PSG data output to CODEC

Note 1:   Bit 2 selects either data from the PSGIN pin or the CDDIN
          pin. That is data from the PSG or from the CODEC ADC. The
          selected data is presented to the matrix and to the adder
          described in note 2. The prototypes and probably early
          systems will not have the digital PSG available. In that
          case the PSGIN and CDDIN pins are connected together and
          the analog PSG output is fed to the CODEC channel 2
          input.

Note 2:   There are two sources of data for the CODEC DAC. Data
          coming from the matrix is enabled into an adder by a
          setting bit 1. The output of the adder is the data sent
          to the CODEC DAC. The other input to the adder is the
          data selected by bit 2 (see note 1).




                FF8938 AUX A Control Field (RW)


D15           D8
D7D0


L16-L19
expn
mute
mux
left gain
right gain


     L16-L19 - Left sample 4 least significant bits

     expn  - Expand

     mute  - Mute
             1 - Mute output

     mux   - Input Mux1
           00 - Channel 1 (microphone)
           11 - Channel 2 (PSG input)

     left gain , right gain

          0000 - 0 dB gain for ADC
             .
             .     ( 1.5dB increments )
             .
          1111 - 22.5 dB gain for ADC

Note 1:   Prototypes and probably early systems will have an analog
          PSG which will be connected to the CODEC ADC channel 2
          input as indicated. Eventually, a digital PSG will be
          used and connected as described under DAC control. Future
          use of channel 2 is reserved.




               FF893A AUX B Control Field (RW) 


D15           D8
D7D0


R16-R19
Left Attn
Right Attn
OPort



     R16-R19 - 4 least significant bits for right sample

     Left Attn - Left Channel D/A Attenuation

          0000 - No attenuation
            .
            .     ( 1.5 dB steps )
            .
          1111 - 22.5 dB attenuation

     Right attn - Right Attenuation in 1.5dB steps

     OPort     - Output Port Control




                 FF893C AUX A Input Field (R)


D15             D8
D7D0


L16-L19
Exp
Vld
Oflw
 sts
rev


     Ls - Left Sample L16-L19
     
     Exp - Expand
           0 - no expansion

     Vld - Valid Data from ADC
           1 - Valid

     Oflw - Overflow
           10 - Overflow Left
           01 - Overflow Right

     Sts - Status
           0000 - no error
           0001 - Invalid control field
           0010 - Invalid sync format
           0011 - Serial clock outof valid range

     rev - Revision Number -> 0000

     iport - Input Port
           - not supported







                 FF893E AUX B Input Field (R)


D15             D8
D7D0


R16-R19
0000
0000
iport


     R16 - R19 Right Sample Least significant bits

     iport - Input Port
         - Not supported




           xxFF8940 General Purpose I/O Control (R)


D15       D8
D7D0


0000
xddd
0000
xccc





           xxFF8940 General Purpose I/O Control (W)


D15       D8
D7D0


XXXXXXXX
XXXX
xccc





             xxFF8942 General Purpose I/O Data (R)


D15        D8
D7D0


0000
xddd
0000
xiii





             xxFF8942 General Purpose I/O Data (W)


D15        D8
D7D0


XXXXXXXX
XXXX
xddd



     ccc - General Purpose I/O Control Register

           1 - Corresponding bit is an output

     iii - GPIOx pin state

     ddd - General Purpose I/O DATA Register (D0 is GPIO0)1

     x   - reserved

Note 1:   The value of the data register bit is driven out when the
          corresponding bit of the control register is 1. The GPIO
          pin is an input when the control register bit is 0. The
          least significant 3 bits of the data register read the
          state of the pin regardless of its programmed direction.


Description

     The Falcon ADMA circuit provides three DMA channels. One
channel is bidirectional and supports the backward compatible ACSI
interface. The other two channels are unidirectional, one into
memory for recording sound, and one out of of memory for playback.
Both the playback and record support 16 bit stereo format. The
playback channel also supports 8 bit stereo and mono formats
compatible with previous Atari products.

     A 4x4 switching matrix and format converter connects the
external sound peripherals and the DMA channels. There are four
sources of sound data, the playback DMA, the DSP SSI port, the
external SSI like port, and the CODEC ADC. There are also four
destinations for sound data, the record DMA, the DSP SSI port, the
external SSI like port, and the CODEC DAC. Each source, except for
the CODEC, can select one of three clock sources. The CODEC can
only select one of two clock sources. The matrix circuitry converts
the data format of the selected source to the destination format.
When data is transfered between either the playback or record DMA
ports and one of the SSI style ports, there is also an option of
gated clock (handshake) or continuous clock modes.


Each receiving device can have its data path connected to any one
source device.
     All the data connections shown above, are actually serial data
paths which include a bit clock, data, and synchronization signal.
There are three possible clock sources in the system:
    
     CLK25 (25.175 MHz)
     CLK32 (32 MHz)
     EXTCLK (external clock)

Each source device must select one of these clocks as its master
clock. The CODEC can use the Internal 25.175MHz, or External clock.
The bit clock is taken from the master clock divided by 4 to 24.
The Sample rate is then the bit rate, divided by 128:

     The maximum data rate of the DMA record or playback channels
is one Megabyte per second each. Since the FIFOs are 32 bytes deep
each sound DMA channel will require bus access approximately every
32us. Communication between the DMA ports and the SSI style ports
can use a handshake to regulate data flow. The port synchronization
signal is input to the DMA port controller in handshake mode. When
the synchronization signal is low (inactive) or when the DMA port
is not ready, the bit rate clock is gated off at the end of the
current transfer to halt data flow. In non-handshake mode, the bit
rate clock runs continuously and the synchronization signal is
output to the port. Data overflow or underruns can occur in non-
handshake mode. The CODEC can only operate in non-handshake mode.

     The SSI style ports use a three wire serial interface to
transfer data. Data transfers use either continuous mode or a
handshaked (gated clock) mode:




Signal
Non-handshake
Handshake


DATA
output
output


CLOCK
output
output


SYNC
output
input


In either mode, data changes on the rising edge of the clock. Data
should be sampled on the falling edge of the clock.

     In Continuous mode there are 128 clock cycles per sample
period. SYNC will go high for the first 16 bits of a sample period
and then low for the remaining 96 bits. In each sample period a
maximum of 8 tracks of 16 bit data can be transferred. Data words
are transmitted MSB first, end-on-end, with no gaps in between
them. The number of words per sample period is determined by the
source device.


     In Handshaked mode SYNC becomes an input. The external device
will pull XO_SYNC high, and if the source device is ready, CLOCK
will become active for 16 cycles (or one word) together with DATA.
SYNC is sampled by the source device at the end of each word. If
SYNC is high and another word is ready to be sent, CLOCK and DATA
will become active for another 16 cycles. A minimum of two clock
periods will always be inserted between data words.


     The CODEC port has 256 bit clock cycles per frame. There are
four sub-frames per frame. Each sub-frame consists of two 32 bit
words. The first half of each word is the 16 bit sample (left
sample first). The second half of each word is a control field for
the CODEC. Only the first two sub-frames of each frame are used.
The contents of the AUX A and AUX B Control registers are output
for the control fields of of the first two sub-frames of the
channel to the CODEC DAC. The contents of the control fields from
the CODEC ADC input channel can be read in the AUX A and AUX B
input registers.

     In the 8-bit modes (playback only) each sample is stored as an
eight bit quantity. The most significant bit is the sign and the
other seven bits are magnitude. In the stereo 8-bit modes there is
one word per sample, the upper byte contains the left channel
sample and the lower byte contains the right channel sample. In the
8-bit mono mode bytes are accessed sequentially. However, they are
still fetched a word at a time. Therefore, there must be an even
number of samples in a frame of mono data.

     In the 16-bit stereo mode each sample is stored as a word in
memory. The most significant bit is the sign and the other fifteen
bits are magnitude. The left channel word is first with the
remaining words alternating right-left-right etc. The DMA channel
into memory (record) can only store samples in the 16 bit form.

     A group of samples is called a frame. A frame may be played
once or can automatically be repeated forever.  Frames occupy a
contiguous block of memory and are specified by their starting and
ending addresses. The ending address is the address of the last
sample + 2 (the address of the word following the last sample). The
SCNT and SINT signals are generated at each frame boundary. Frames
may be linked together by defining a new frame while the current
frame is being played. The new frame will begin at the end of the
current frame.

     The DMA channel does not determine how the samples are
defined, only their location in memory and the order in which they
are handled. The data need not be digitized sound at all.

     The MICROWIRE interface has been deleted from the current
design. The Microwire registers are simulated in the current
circuit only to prevent older software attempting to use the
interface from locking up.

     Three general purpose I/O signals have been added. These are
programmable as inputs or outputs.