[PageStream 2 document MEGASERV.DOC: 8.50 x 11.00 in, 729 objects] --- Page 1 --- [283 drawing objects, see MEGASERV.DOC.p001.svg] SECTION ONE INTRODUCTION 1.1 OVERVIEW The Atari® MEGA STE™ is the newest enhancement in the series of Atari ST™ computers. The MEGA STE is upward compatible with the Atari STE™ and is designed as an integrated unit with processor, memory, and I/O, floppy disk drive, and power supply in one package. The MegaSTer provides either 1, 2, or 4 Mbytes of RAM memory and 256 Kbytes of ROM memory. A 16 Kbyte cache memory is also provided. The floppy disk drive storage capacity is 720 Kbyte (formatted). An optional 1.44 Mbyte (formatted) floppy, hard disk drive, and floating point coprocessor can also be added. 1.2 MAIN COMPONENTS • Main Board • Power Supply • Floppy Disk Drive • Optional Hard Disk Drive • Keyboard • Mouse • Plastic Case (upper and lower) 1.3 CASE DESIGN The front of the MEGA STE contains a Power LED and the floppy disk drive with an eject button and busy LED. An optional hard disk can also be installed and contains its own busy LED. Power LED Floppy Disk Eject Button Hard Disk Busy LED Busy LED Front View --- Page 2 --- [421 drawing objects, see MEGASERV.DOC.p002.svg] The left side of the MEGA STE case contains the following items from left to right. Reset button, LAN connector, MIDI out jack, MIDI in jack, ROM cartridge port, and keyboard jack. LEFT SIDE VIEW The rear of the MegaSTer contains the following items from left to right. External floppy jack, monitor jack, TV jack, Serial 2 or VME slot, external ACSI interface connector, printer connector, modem 1 connector, on/off switch, power plug, modem 2 connector, fan, audio R connector, and audio L connector. REAR VIEW 1.4 POWER SUPPLY 1.4.1 Power Supply Rating The MegaSTer has an integral switching power supply providing 65 watts of power. The supply can accept AC input of 100-240VAC at 2A, 50/60Hz. The power supply provides the following voltages and currents to the system: Voltage Current +5V 7A -5V 2A +12V 0.4A -12V 0.3A SECTION TWO THEORY OF OPERATION 2.1 OVERVIEW The MegaSTer is an upward compatible extension of the Atari STr architecture. A VME bus has been included in the MegaSTer for expansion. The hardware is composed of a main system (central processing unit and support chips), audio/video subsystem, and several I/O subsystems. Main System MC68000 processor running at 8/16 MHz Optional MC68881 or MC68882 coprocessor 256 Kbytes of ROM 1024, 2048 or 4096 Kbytes of RAM 16 Kbytes of cache RAM Processor speed/cache control Interrupt mask, status, and control (MFP and SCU) System timing and Bus control (GSTMCU, PALs U3, U6, U2) DMA support Battery backed-up Real-time clock Audio/Video Subsystem Bit Mapped video display using 32 Kbytes of RAM relocatable anywhere in memory. Three available display modes: 320 X 200 16 out of 4096 colors 640 X 200 4 out of 4096 colors 640 X 400 monochromeMonitor interfaces include: RGB Monochrome Composite Television Audio outputs: Programmable sound generator DMA sound output I/O Subsystems Floppy disk interface High-speed serial ports MFP serial port Parallel printer interface Intelligent keyboard interface Mouse and Joystick interface Hard disk interface Musical Instrument Digital Interface (MIDI) VME bus 2.2 MAIN SYSTEM The hardware contained in the main system of the Atari MegaSTer are the processor, optional coprocessor, ROM, RAM, cache RAM, system speed and cache control, Interrupt control (SCU and MFP), Timing and Bus control (GSTMCU), DMA support, Real-time clock, and ACSI interface. 2.2.1 Processor U007 Pg. 1 The processor used in the Atari MegaSTer system is a 16 MHz Motorolar MC68000 with a 32-bit internal architecture, 16-bit external data bus, and a 24-bit address bus. The processor can be operated at either 8 or 16 MHz. 2.2.2 Coprocessor (Optional) UB02 Pg. 11 A socket is provided in the MegaSTer for an optional Motorolar MC68881 or high performance MC68882 floating point coprocessor. The coprocessor is clocked at 16 MHz independent of the speed at which the processor is running. The processor does not directly support the coprocessor but accesses it as an I/O device with memory type instructions via its address and data buses. 2.2.2.1 Coprocessor Control Signal Generation UB01 Pg. 11 Chip select and data strobe signals for the coprocessor are generated by a PAL in location UB01. 2.2.3 ROM U206, U207 Pg. 2 The system contains two 128 Kbyte ROMs for a total of 256 Kbyte of access space. Since system bus access is 16-bits wide, both ROMs must be present for proper operation. Included in the tasks the ROM performs is system initialization and boot code from the floppy, hard disk, ACSI interface, and network. The ROM also contains a language specific implementation of the TOS operating system. 2.2.4 RAM U701, U702, U703, U704 Pg. 7 The MegaSTer includes either 1, 2, or 4 Mbytes of RAM used for both system and video. The RAM is implemented with 8-bit SIMMs (Single Inline Memory Module) and must be installed in matching pairs. Memory accesses to the RAM are interleaved between the Memory Controller and the Video Controller in 250ns time slices. During display cycles, the processor is prevented from accessing the RAM. However, the processor will be allotted the next 250ns time slice. Additional memory can be installed in the system via VME memory cards. Up to 4 Mbytes of additional 16-bit wide RAM can be installed in this way. VME memory will typically run slower than on-board system memory because all accesses incur an additional wait state.RAM memory map: Address Usage 000008 - 000800 System memory (privileged access) 000800 - 07FFFF Low Bank (1 Mbyte systems) 080000 - 0FFFFF High Bank (1 Mbyte systems) 000800 - 0FFFFF Low Bank (2 Mbyte systems) 100000 - 1FFFFF High Bank (2 Mbyte systems) 000800 - 1FFFFF Low bank (4 Mbyte systems) 1FFFFF - 3FFFFF High bank (4 Mbyte systems) 2.2.5 Cache RAM U004, U005, U008, U009 Pg. 1 Cache RAM consists of 16 Kbytes of fast SRAM memory. RAM cycles are cached using 8K words, which are 16-bits wide. This permits cache-hit memory cycles to run at zero wait states and without taking a cycle on the system bus when the processor is running at 16 MHz. 2.2.6 System Control Unit (SCU) U801 Pg. 8 The SCU provides several system support functions including interrupt masking and status reporting, interrupt generation, and bus timeout detection. 2.2.6.1 Interrupt Mask and Current Status The SCU contains two registers used to mask interrupts to the processor. These registers, in effect, screen the interrupts from both main system devices and VME bus devices and present them, when enabled (not masked), to the processor. Masked interrupts (not enabled) are not presented and therefore not seen by the processor. These registers are cleared at power up or reset, disabling all interrupts. The SCU also contains a register which latches the current state of the seven interrupt request levels from each one of the sources. This register shows the state of the interrupt lines before they are ANDed with the mask registers.2.2.6.2 Interrupt Generation The system can write to an I/O address to generate a level 1 autovectored interrupt to the processor. The SCU is hardwired to the following interrupt scheme: Only interrupt levels 5 and 6 have external interrupt acknowledge (IACK) pins and are capable of generating vectored interrupts to the system. SCU generated interrupts IRQ1 and IRQ3 are hardwired to the corresponding priorities and are always autovectored. The VMEbus ACFAIL generates an IRQ7 interrupt to the processor. The only other source of IRQ7 interrupt is from a VMEbus card. 2.2.6.3 Bus Timer The SCU implements a bus timer so that if a bus cycle is not terminated within 16us, the SCU will generate a bus error signal. 2.2.6.4 Processor/Cache Control There is a register implemented in the SCU used to select processor speed (8/16 MHz) and enable cache memory. The address decode for the register is done by PAL UA02 (Pg. 10). Bit 0 enables the cache and bit 1 selects the processor speed. The clock control signal is generated by PAL U407 (Pg. 4) and supplied to PAL U11 (Pg. 1). The cache enable signal is also supplied to PAL U11. These signals are the multiplexed to the processor clock pin and cache enable pins of the SRAM by PAL U12 (Pg. 1). 2.2.7 68901 MFP U306 Pg. 3 2.2.7.1 MFP Interrupt Control The 68901 MFP handles up to 16 interrupts. Currently all but one are used. Each interrupt can be masked off or disabled by programming the MFP. The 8 inputs are also directly readable by the CPU. When the MFP receives an interrupt input, or generates an input internally, if the interrupt is enabled, MPINT will be driven low. When the CPU is ready to respond, it signals interrupt acknowledge (PC0-PC2 high and VMA low) and GSTMCU will assert IACK (interrupt acknowledge). The MFP will assert DTACK and put a vector number on the data bus, which the CPU will read and use to calculate the address of the interrupt routine.The interrupts controlled by the MFP are: monochrome monitor detect (MONOMON), RS-232 (Including CTS, DCD, and RI), floppy and hard disk (FDINT and HDINT respectively), parallel port BUSY, display enable (DE, which equals the start of the display line), 6850 IRQ's for keyboard and MIDI data, and MFP timers. Not all I/O operations are interrupts. The CPU can also poll the MFP while waiting for an operation to complete. The MFP also contains four timers. These are used by the Operating System for event timing and by the RS-232 port for transmit and receive clocks. 2.2.8 System Timing and Bus Control GSTMCU U501 Pg. 5 PALs U2, U3, and U6 Pg. 11 The GSTMCU is an integral part of the system and is involved in almost every operation in the computer. The functions performed by the GSTMCU include clock dividers, video timing, signal and bus arbitration, memory control, and chip selects. 2.2.8.1 Clock Dividers The clock dividers within the GSTMCU are used to take the 16 MHz input and divide it into 4 MHz, 8 MHz, and 500 kHz clocks for use by other devices in the system. 2.2.8.2 Video Timing The GSTMCU outputs the signals BLANK, DE (Display Enable), VSYNC, and HSYNC to generate system video. There is also a read/write register within the GSTMCU which is used to configure for 50, 60, or 71 Hz monitor operation (done by software). 2.2.8.3 Signal and Bus Arbitration The GSTMCU arbitrates the bus during DMA cycles to prevent the processor and DMA controller from interfering with one another. PAL U6 synchronizes the bus error and data transfer acknowledge signals to the processor. PAL U3 is a data strobe state machine used to generate both upper and lower data strobes on byte reads when cache RAM is enabled. PAL U2 is used to latch latch data strobe, address strobe, and read/write signals to the processor.2.2.8.4 Memory Control The GSTMCU takes addresses from the address bus and coverts them to Row Address Strobe (RAS) and Column Address Strobe (CAS) signals to control all RAM accesses. The Memory Controller internal to this device is also responsible for refreshing the DRAM (dynamic RAM), loading the Video Shifter with display data, and sending or receiving data during DMA cycles. 2.2.8.5 Chip Selects The GSTMCU decodes addresses and generates chip selects to the 6850's, 68901 MFP, DMA Controller, Programmable Sound Generator, internal Memory Controller, and ROMs. It receives signals from the MFP, DMA, and Memory Controller to synchronize data transfers. The GSTMCU also decodes the addresses necessary to enable the RAM and ROM. 2.2.9 DMA Support U404 Pg. 4 Direct memory access is provided to support both low speed (250 to 500 kilobits/sec) and high speed (up to 8 Megabits/sec) 8-bit device controllers. The floppy disk transfers at low speed and the hard disk (or other devices on the hard disk port) transfer at high speed. For DMA to take place, the Memory Controller is given the address of where to take data from or put data in RAM, the DMA Controller is set up (with channel, high or low speed, and how many bytes) and the peripheral is given a command to send or receive data. The entire block of data (the size must be given to the DMA Controller and the peripheral before the operation starts) is then transferred to or from memory without intervention by the CPU. 2.2.10 Real-time Clock U402 Pg. 4 The MegaSTer system includes a Real-time Clock chip. When the system is powered on the real-time clock is powered by the main PCB power supply. In the event of a power failure, or when the system is powered off, the real-time clock is powered by a 3.6v lithium battery. This allows the date and time to be maintained even when there is no power to the unit. The real-time clock provides time of day (down to one second resolution) and date. The RTC is provided with a 32.760 kHz oscillator that is independent of all other system clocks. The chip is accessed through 32 4-bit registers accessed in two banks. Bank 0 allows reading and setting of each digit of the date and time. It also allows access to test and control registers within the device. Bank 1 allows setting the digits of the alarm function and controls the mode of operation of the clock. 2.3 AUDIO/VIDEO SUBSYSTEM 2.3.1 Video Subsystem U501, U502, U205, U503 Pg. 5 The video subsystem consists of the video display memory (an arbitrary block of RAM starting on any word boundary), the GSTMCU U501, a graphics control chip GSTSHFTR U502, a graphics coprocessor chip STB U205, some discrete components to drive the video output, and an RF modulator U503. The role of the GSTMCU has already been covered in section 2.2.8.2 2.3.1.1 GSTSHFTR Video Shifter U502 Pg. 5 There are 16 color palette registers in the shifter. All 16 may be used in low resolution (320 X 200). Four may be used in medium resolution (640 X 200), and one may be used in monochrome (640 X 400) high resolution (actually only bit 0 of register 0 is used for inverse/normal video). Contained in each entry are twelve-bits of color; four-bits each for red, green, and blue. Therefore there are 16 X 16 X 16 or 4096 colors possible for each entry. For a given pixel, the color which is displayed is taken from the palette referred to by getting information from each logical plane (see the description of video display in section 2.3.1.3). The shifter will output the red, blue, and green levels specified by that palette. Note that there are four outputs for each color. Each output is either on or off. This makes the number of possible output levels 2 to the 4th power or 16. The four outputs are summed through a resistor network to proportion the voltage level to give sixteen equal steps. In monochrome mode, the color palettes are bypassed and there is a separate output. 2.3.1.2 Graphics coprocessor STB U205 Pg. 2 The graphics coprocessor (Blitter) handles the extra burden of graphics video generation on the processor. The STB performs bit aligned block transfers required in graphics generation, adding to the capability of the processor which only works on word or byte boundaries. The STB also provides barrel shift functions that are not contained in the processor. 2.3.1.3 Video Display Memory Display memory is part of main memory with the physical screen origin located at the top left corner of the screen. Display memory is configured as 1, 2, or 4 logical planes interwoven by 16-bit words into contiguous memory to form one 32,000 byte physical plane starting at any 2-byte boundary. The starting address of display memory is placed in the Memory Controller's Video Base High, Video Base Mid, and Video Base Low registers by the Operating System or application. This register is loaded into the Video Address counter (high, mid, and low) at the beginning of each frame. The address counter is incremented as the Bit Map planes are read. The Memory Controller will load display information into the Video Shifter 16 bits at a time, and the Video Shifter will decode this information to generate a serial display stream. In monochrome mode, each bit represents one pixel on or off. In color, bits are combined from each plane to generate the correct level of red, green, and blue. For example, in low resolution (4 planes) four words are loaded into the Video Shifter for each word (16 pixels) displayed on the screen. The Video Shifter combines bit 0 from each word to form a four bit number (0-15), and takes the color from the palette referenced by that number (e.g. 0101 = 5, use color from palette register 5) and outputs those levels, then takes bit 1 from each plane and outputs the color from the palette referenced by those four bits, etc. 2.3.1.4 Television Interface Pg. 5 The MC1377 takes the red, green, and blue video signals from the emitter followers Q501, Q502, and Q503 and adds them to the HSYNC and VSYNC signals to form composite video. The composite signal is then modulated onto an RF carrier and locked onto the color burst frequency by a phase locked loop. The RF video is then output to an RCA type jack on the back of the computer. 2.3.1.5 Horizontal Scrolling Two additional registers implement a horizontal smooth scroll capability. The horizontal pixel scroll register holds a pixel offset value from 0-15 at which to begin display. Increasing this value by one will scroll the whole display one pixel to the left. The extra line width register contains a number of words that is added to the ending address of each display line to get the beginning address of the next display line. It puts an undisplayed area to the right of the video screen. By using these two registers the video screen can be used as a horizontally scrolling window.2.3.1.6 GENLOCK and the MegaSTer The MegaSTer has the ability to accept external sync. This was done to allow synchronization of the MegaSTer video with an external source. In order to do this reliably, the system clock must also be phase-locked to the input sync signal. To do this pin three of the monitor connector must be grounded. The clock can then be input on pin four of the monitor connector. The internal frequency of this clock is 32.215905 MHz for NTSC and 32.084988 MHz for PAL. 2.3.1.7 Monitor Input Levels HSYNC - TTL level, negative, 3.3 K ohm VSYNC - TTL level, negative, 3.3 K ohm Monochrome - digital 1.0V p-p, 75 ohm RGB - analog 0-1.0V p-p, 75 ohm Audio - 1.0V p-p, 1 K ohm 2.3.1.7 Monitor Connector The video output is provided on a 13-pin DIN type connector located on the back of the computer. The connector is compatible with the STr and STer series systems. Either color or monochrome monitors can be used. The pinout of this connector is as follows: Pin Function 1 Audio Out 2 Composite Video 3 External Clock Select (Pull low for external clock on pin 4) 4 Monochrome Monitor Detect (When used for GENLOCK becomes clock) 5 Audio Input 6 Green 7 Red 8 Peritel Power 9 HSYNC 10 Blue 11 Monochrome Out 12 VSYNC 13 Ground2.3.2 Audio Subsystem The MegaSTer extends the present audio subsystem of the Atari STr computer. It mixes the output of the existing ST programmable sound generator (PSG) with a DMA-driven dual channel digital to analog subsystem. The MegaSTer combines these two sources and sends the resulting audio through the audio output pin of the monitor connector. In addition, the audio output can be connected to an external stereo amplifier for high-fidelity sound. 2.3.2.1 Programmable Sound Generator U305 Pg. 3, U608 Pg. 6 The programmable sound generator (U305) produces music synthesis, sound effects, and audio feedback. With an applied clock of 2 MHz, the PSG is capable of providing frequencies from 30 Hz to 112 kHz. The PSG has the ability to perform using three separate voice channels. The three sound channel outputs are mixed together and sent to the LMC1992 volume and tone control chip (U608). 2.3.2.2 DMA Sound Sound in the form of digitized samples is stored in the system memory. These samples are fetched from dual purpose memory during horizontal blanking cycles and provided to a Digital to Analog Converter (DAC) at a constant sample frequency specified by the user. The output of the DAC is then low pass filtered to a frequency equal to forty percent of the sample frequency by a four pole switched capacitor low pass filter. The signal is further filtered by a two pole fixed frequency (15 kHz) low pass filter and sent to the LMC1992 Volume and Tone Control chip. The signal is then made available to two RCA type jacks at the back of the computer as well as the audio output pin of the monitor connector. 2.4 I/O SUBSYSTEMS 2.4.1 Floppy Disk Interface U405 Pg. 4 The floppy disk subsystem is designed around the Floppy Disk Controller supporting up to two daisy-chained disk drives. One internal and one external drive can be connected to the system. The subsystem interfaces to the RAM through the ACSI DMA controller. Commands and arguments are sent to the FDC by first writing to the DMA Mode Control Register to select the desired FDC register and then writing the data bytes.The standard drive for the system is a 720 Kbyte (capacity after formatting) 3 1/2-inch floppy disk. The internal drive cabling supports the Disk Change Line signal from the floppy drive and is read when the drive is selected, and is asserted when power is applied or a diskette is removed from the drive. The signal can be cleared by issuing a step command to the drive. Two clock speeds are provided to support both low and high density floppy drives. The decode for the register that hold the selection id done by PAL UA02 (Pg. 11). The signal is sent to PAL U407 (Pg. 4) where the proper clock is sent to the floppy disk controller. 2.4.1.1 Floppy Port Pinout Pin Function 1 Read Data 2 Side 0 Select 3 Logic Ground 4 Index Pulse 5 Drive 0 Select 6 Drive 1 Select 7 Logic Ground 8 Motor On 9 Direction In 10 Step 11 Write Data 12 Write Gate 13 Track 00 14 Write Protect2.4.1.2 Internal Floppy Disk Drive Connector Pinout Pin Function 1-33 Odd Ground 2 FDDS 4 No Connect 6 No Connect 8 Index 10 Drive 0 Select 12 Drive 1 Select 14 No Connect 16 Motor On 18 Direction In 20 Step 22 Write Data 24 Write Gate 26 Track 00 28 Write Protect 30 Read Data 32 Side 0 Select 34 No Connect 2.4.2 High Speed Serial Ports SCC UA04 Pg 11 The MegaSTer contains an 85C30 Serial Communications Controller (SCC) that provides a dual channel, multi-protocol device that provides two serial ports. Port A can be used as either a network port or a standard slow speed RS232C serial port. The input/output of port A is routed to the appropriate connector, either an 8-pin mini-DIN or DB-9P, by setting a bit in a register (user application or Operating System). The output pins on the unselected port remain inactive Port B is configured to be a low speed standard RS232C serial port that can be used for connecting a modem or local mainframe. The input/output of Port B is connected to a DB-9P connector and modem control signals are derived directly from the 85C30 Port B control lines. Port B can also operate with split transmit and receive baud rates. The PCLK input to the SCC is rated at 8 MHz. The RTXCA and RTXCB input is provided with a 1.672 MHz clock. The TRXCA input comes from the LAN connector, and the TRXCB input is rated at 2.4576 MHz. Control signals are sent to the SCC by PAL UA03 (Pg. 11).2.4.2.1 SCC RS-232 Pinouts Port A Pin Function 1 Carrier Detect (In) 2 Receive Data (In) 3 Transmit Data (Out) 4 Data Terminal Ready (Out) 5 Ground 6 Data Set Ready (In) 7 Request to Send (Out) 8 Clear to Send (In) 9 No Connect Port B Pin Function 1 Carrier Detect (In) 2 Receive Data (In) 3 Transmit Data (Out) 4 Data Terminal Ready (Out) 5 Ground 6 Data Set Ready (In) 7 Request to Send (Out) 8 Clear to Send (In) 9 No Connect 2.4.2.2 SCC LAN Connector Pinout Port A LAN Connector Pin Function 1 Output Handshake (DTR, RS423) 2 Input Handshake (TRXCA external clock) 3 Transmit Data- 4 Ground 5 Receive Data- 6 Transmit Data+ 7 (Reserved) 8 Receive Data+ 2.4.3 MFP Serial Port Pg. 3 The 68901 MFP also provides a slow speed RS232C serial port to the system. The baud rate clock for the MFP serial port transmitter and receiver is derived from the timer D output of the MFP. Given the MFP's 2.4576 MHz clock, baud rates up to 19.2Kbaud can be supported. The MFP serial port is connected to a DB-9P connector and contains a complete complement of modem control lines, (excluding Data Set Ready, pin 6). 2.4.3.1 MFP Serial Port Pinout Pin Function 1 Carrier Detect (In) 2 Receive Data (In) 3 Transmit Data (Out) 4 Data Terminal Ready (Out) 5 Ground 6 No Connect 7 Request to Send (Out) 8 Clear to Send (In) 9 Ring Indicator (In) 2.4.4 Parallel Interface U305 Pg. 3 The parallel interface is implemented through the programmable sound generator chip. It is a subset of the Centronicsr standard and is output to a DB25 connector. The Centronics STROBE signal is generated from the PSG bit. The Centronics BUSY signal is connected to one of the parallel input lines of the MFP (U404) to permit interrupt driven printing. Eight bits of read/write data are handled through I/O port B on the PSG at a typical transfer rate exceeding 4 Kbytes per second. 2.4.4.1 Parallel Port Pinout Pin Function 1 STROBE 2 Data 0 3 Data 1 4 Data 2 5 Data 3 6 Data 4 7 Data 5 8 Data 6 9 Data 7 10 Not Connected 11 BUSY 12-17 Not Connected 18-25 Ground 2.4.5 Keyboard Interface The keyboard transmits encoded make/break key scan codes (with two key rollover), mouse/trackball data, joystick data, and time-of-day. The keyboard receives commands and sends data via bidirectional communication implemented with an MC6850 Asynchronous Communications Interface Adapter (ACIA) and located in the keyboard. The data transfer rate is 7812.5 bits per second. The keyboard interfaces through a 6-pin telephone style jack.2.4.5.1 Keyboard Connector Pinout Pin Function 1 +5V 2 +5V 3 Transmit 4 Receive 5 Ground 6 Ground 2.4.6 Mouse and Joystick Interface The Atari two-button mouse is a mechanical, opto-mechanical, or optical mouse with the minimal performance characteristics of 100 counts/inch, maximum velocity of 10 inches per second, and maximum pulse phase error of 50 %. The joystick is a four direction switch-type joystick with one fire button. The mouse and joystick are connected via two DB-9P connectors located on either side of the keyboard. A mouse or joystick can be connected on the right side of the keyboard. The connector on the left side of the keyboard is for joystick only. 2.4.6.1 Mouse/Joystick Connector Pinout Pin Function 1 Up XB 2 Down XA 3 Left YA 4 Right YB 5 Not Connected 6 Fire/Left Button 7 +5VDC 8 Ground 9 JOY1/Fire Right Button 2.4.6.2 Joystick Connector Pinout Pin Function 1 Up 2 Down 3 Left 4 Right 5 Reserved 6 Fire Button 7 +5VDC 8 Ground 9 Not Connected 2.4.7 Hard Disk Interface Optional hard disks can be added to the system. The hard disk interfaces through the ACSI bus via a SCSI paddle board which plugs into the motherboard. The controller sends commands and data to the hard disk by way of the ACSI (Atari Computer System Interface) bus. All transfers to the hard disk are via DMA and the SCSI paddle board. DMA transfers are controlled by the SCSI paddle board via the HDRQ signal. To access the SCSI paddle board the HDCS (Hard Disk Chip Select) signal is driven low and the CA1 signal to be asserted. The DMA support chip must respond with ACK low to acknowledge that data is on the bus or has been read from the bus. The Memory Controller internal to the GSTMCU then works with the DMA controller to write or read data from or into memory. Transfers can take place at up to 1 Mbyte per second.2.4.7.1 External Hard Disk Pinout (ACSI) Pin Function 1 Data 0 2 Data 1 3 Data 2 4 Data 3 5 Data 4 6 Data 5 7 Data 6 8 Data 7 9 Chip Select 10 Interrupt Request 11 Ground 12 Reset 13 Ground 14 Acknowledge 15 Ground 16 A1 17 Ground 18 Read/Write 19 Data Request 2.4.8 ROM Cartridge The MegaSTer contains a ROM cartridge port that is fully compatible with the Atari STr cartridges. The cartridge is physically connected through a 40-pin edge connector located on the left side of the case. ROM cartridges are mapped to a 128 Kbyte area starting at address FA0000 and extending to FB8FFF. 2.4.9 Musical Instrument Digital Interface (MIDI) The MegaSTer is also equipped with a Musical Instrument Digital Interface (MIDI) which provides high speed serial communication of musical data to and from sophisticated synthesizer devices. The Musical Instrument Digital Interface (MIDI) allows the integration of the MegaSTer with music synthesizers, sequencers, drum boxes, and other devices possessing MIDI interfaces. High speed (31.25 Kbaud) asynchronous current loop serial communication of keyboard and program information is provided by two ports, MIDI OUT and MIDI IN (MIDI OUT also supports the optional MIDI THRU port). MIDI specifies that data consist of eight data bits, one start bit, and one stop bit. The MIDI OUT and MIDI IN connector pinouts are as follows: MIDI OUT Pin Function 1 THRU Transmit Data 2 Shield Ground 3 THRU Loop Return 4 OUT Transmit Data 5 OUT Loop Return MIDI IN Pin Function 1 Not Connected 2 Not Connected 3 Not Connected 4 IN Receive Data 5 IN Loop Return 2.4.10 VME Bus Pg. 9, 10 The VME bus is provided for system expansion. The bus is composed of 23 address lines and 16 data lines. Control for the bus is provided by PAL U903 (Pg. 9) and U904 (Pg. 9). External interrupt requests to the VME bus are handled by the SCU IC U801 (Pg. 8). The VME bus in the MegaSTer complies with the Vita C.1 specification. It supports A24/D16 or A16/D16 slave cards only.2.5 SYSTEM STARTUP After a RESET (power-up or reset button) the 68000 will start executing at the address pointed to by locations 4-7, which is ROM (GSTMCU maps the first 8 bytes of ROM at E00000-7 into addresses 0-7). Location 000004 points to the start of the operating system code in ROM. The following sequence is then executed: Perform a reset instruction (outputs a reset pulse to reset hardware registers). Read the longword at cartridge address FA0000. If the data read is a "magic number", execute from the cartridge (ROM cartridge instructions take over here). If not, continue. Check for a warm start (see if RAM locations contain valid data), initialize the memory controller. Initialize the PSG chip, deselect disk drives. Initialize color palettes and set screen address. If not a warm start, zero memory. Set up operating system variables in RAM. Set up exception vectors. Initialize MFP. Set screen resolution. Attempt to boot floppy; attempt to boot hard disk; run program if succeeded. If no boot disk, the 256K boot ROM will bring up the desktop. 2.6 SYSTEM ERRORS The 68000 has a feature called exception processing, which takes place when an interrupt or bus error is indicated by external logic, when the CPU detects an error internally, or when certain types of instructions are executed. An exception will cause the CPU to fetch a vector (address to a routine) from RAM and start processing at the routine pointed to by the vector. Exception vectors are initialized by the operating system. Those exceptions which do not have legitimate occurrences (interrupts being legitimate) have vectors pointing to a general purpose routine which will display some number of bombs showing on the screen. The number of bombs equals the number of the exception which occurred. System errors may or may not be recoverable. Errors in loading files from disk may cause the system to crash, necessitating a reset. Verify the diskette and disk drive before attempting to repair the computer. 2.6.1 Number of Bombs and Meaning Bombs Meaning 2 Bus Error. GSTMCU (U501) asserted bus error. This condition can be due to faulty MFP (U306), RAM (U701, U702, U703, U704), ROM (U206, U207), PSG (U305), or a short/open on the PCBA address/data lines. 3 Address Error. Processor attempted to access word or long word sized data on an odd address. 4 Illegal Instruction. Processor fetched an instruction from ROM or RAM which was not a legal instruction. 5 Zero Divide. Processor was asked to perform a division by zero. 6 Chk Instruction. This is a legal instruction, if software uses this, it must install a handler. 7 Trapv Instruction. See Chk instruction. 8 Privilege Violation. CPU was in user mode, tried to execute a supervisor instruction. 9 Trace. If trace bit is set in the status register, the CPU will execute this exception after every instruction. Used to debug software. 10 Line 1010 Emulator. CPU read pattern 1010 as an instruction. Provided to allow user to emulate his own instructions. 11 Line 1111 Emulator. See Line 1010 Emulator. 12-23 Unassigned, should be no occurrence. 24 Spurious Interrupt. Bus error during interrupt processing. 25-31 Autovector Interrupt. Even numbered vectors are used, others should have no occurrence. Bombs Meaning 32-63 TRAP Instruction. CPU read instruction which forced exception processing. 64-79 MFP interrupts. 80-255 User interrupts. 2.7 Atari MegaSTe Block Diagram SECTION THREE TESTING 3.1 OVERVIEW This section pertains to the test equipment, diagnostic software, and test procedures used to verify correct operation and repair of the MegaSTer computer. The diagnostic cartridge should be used if possible. If the unit gives no display or RS232 output when running the cartridge, see "Troubleshooting a Dead Unit" below. Since the level of complexity in the MegaSTer system is high, it should not be expected that this document can cover all possible problems or pinpoint the causes; rather, the intent here is to give a systematic approach which a technician can use to narrow down a problem to its most likely source. Experience in troubleshooting computer systems is assumed. Knowledge of the 68000 processor is helpful. Economics will be an important consideration; due to the low cost of the MegaSTer computer, little time can be justified in troubleshooting down to the component level when it may be cheaper to replace the functional subassembly. Many of the more expensive (and critical) components are socketed, making verification and replacement faster. 3.2 TEST EQUIPMENT The following equipment will be needed to test the MegaSTer computer: Atari SC1224 RGB Monitor Atari SM124 Monochrome Monitor SF314 External Floppy Disk Drive MegaSTer Port Test Fixture RS232 Loop-Back Connector (3) MIDI Loop-Back Cable MegaSTer Test Diagnostic Cartridge Rev. 1.3 Blank Double Sided 3 1/2-inch Diskettes (2) LAN Loopback ConnectorOptional (for troubleshooting): RS232 terminal (or STer with VT52 emulator) RS232 Null Modem Cable In addition, the following items may be required to troubleshoot and repair the unit: 2 Channel 100MHz Oscilloscope Small Hand Tools Spare Parts 3.3 TEST CONFIGURATION With the power switch off, install the Diagnostic Cartridge with the label facing up. IMPORTANT--if the cartridge does not have the plastic enclosure, BE SURE THE CARTRIDGE IS INSTALLED WITH THE CHIPS FACING DOWN). Connect cables from the STer test fixture into the hard disk port, parallel port, and joystick/mouse ports. The joystick cables should be plugged in so that, if the fixture ports were directly facing the computer ports, the cables would not be crossed. Plug the MIDI loopback cable and LAN loopback connector into their ports. Plug the color monitor into the monitor output (a monochrome can be used instead). NOTE: THE RS232 LOOPBACK CONNECTORS SHOULD ONLY BE PLUGGED IN AFTER THE MENU IS DISPLAYED. Make sure the switch on the STer test fixture is in the position marked INT, otherwise the program will not proceed past the initialization. The other position is GENLOCK. The GENLOCK test is discussed later in section 3.4.4. Power on the unit. Some tests will be run automatically; in a few seconds the menu screen should appear. If the screen appears, skip down to "MegaSTer Diagnostic Cartridge", below. If not, read next section "Troubleshooting a Dead Unit".3.4 TROUBLESHOOTING A DEAD UNIT In the event that the system is correctly configured and powered on and no display appears, this is the procedure to use for determining the problem. This assumes elementary steps have been taken, such as checking the power LED to verify the unit is powered on and making sure the monitor is working. If the LED in the forward left corner is not illuminated, check the power supply voltages first. If voltages require adjusting, perform the adjustments. If the power supply is defective, replace the supply, then if the LED is still not illuminated, check to see if it is defective. Connect a dumb terminal to the RS232 port of the unit under test (U.U.T.). You can use an STer running the VT52 terminal emulator program. Please see the owner's manual for setting up VT52. The cable should connect pin 3 (serial out) of the U.U.T to pin 2 (serial in) of the terminal, and vice versa. Connect pin 7 (ground) to pin 7. The terminal should be set up for 9600 bps, 8 bits of data, 1 stop bit, no parity (this is the default condition for the VT52 emulator). Insert the Diagnostic Cartridge into the U.U.T., and power on the unit. If the Diagnostic Cartridge messages appear on the display of the terminal, use the diagnostic to troubleshoot the computer. If not, the computer will have to be disassembled to troubleshoot. Refer to "MegaSTer Diagnostic Cartridge" below for information on using the cartridge. If no activity is seen on the RS232 port or display, continue with (2) below. Disassemble the computer so that the printed circuit board is exposed (see Section 4, Disassembly). Power up the computer. Using an oscilloscope, verify the 8 MHz clock to the 68000 CPU (pin 15). Replace oscillator if necessary. Then check pin 17 (HALT) of the 68000 CPU. It should be a TTL high. If so, go on to 3 below. If not, the CPU is halted. The reasons may be: (1) bad reset circuit, (2) double bus error, 3) bad CPU. Check (1) by observing signal on input of the two inverters on the HALT line. Check (2) by observing pin 22 of the CPU (BERR) as the unit is powered on. It should be high always. If there are logic low pulses, some component is malfunctioning and GSTMCU is generating the error. Verify the clocks to GSTMCU and replace these components to verify them (if socketed). If still failing, the CPU is unable to read ROM or there is a component which is not responding to a read or write by the CPU, probably the MFP 68901 or DMA Controller. The MFP should respond to an MFPCS with DTACK. The DMA chip should respond to FCS by asserting RDY. There is no way to check for a bad 68000 other than by elimination of the other two possibilities, although a hot CPU (too hot to touch for more than a second) strongly indicates a bad CPU.If the CPU is not halted, it should be reading instructions from ROM cartridge, if installed, and data and address lines will be toggling. (If not, replace CPU.) At this point, there is the possibility that both the video and RS232 subsystems are failing. Verify the output of the MFP chip (pin 9) while powering on the unit with the cartridge installed. If data is being sent, trace it through the 1488 driver. Note that + and - 12v. is required for RS232. If all looks good, here may be something wrong with the connection to the terminal. Verify also the output of the Video Shifter. If using an RGB monitor, check the outputs to the summing resistors for R, G, and B. Note that if BLANK is not going high, no picture will be possible. If using monochrome, check output pin 50. Also check the input to the MFP, pin 32, MONOMON-. Note that if the CPU does not read a low on this signal on power-up, it will cause RGB output on the Video Shifter. If the Video Shifter is outputting a signal, but the picture is unreadable, there is probably a problem with screen RAM. The cartridge should be used to diagnose this problem, with the RS232 terminal as a display device. 3.4 MegaSTer DIAGNOSTIC CARTRIDGE The MegaSTer Diagnostic Cartridge is used to detect and isolate component failures in the MegaSTer computers. This document refers to revision 1.3. Users of earlier versions should refer to the appropriate Troubleshooting Guide. This section gives a brief guide to use with a description of each test, error codes or pass/fail criteria, and recommendations on repair. 3.4.1 Power-up The diagnostic program performs several tests on power-up. In particular, the message "Testing MFP, GSTMCU timing, Video will appear, and the screen will appear scrambled for a few seconds before the menu is printed. The screen will turn red (dark background in monochrome) if an error occurs in the initial testing, with a message indicating the failure. The lowest 2 Kbytes of RAM is tested on power-up; if a location fails, the error will be printed to the RS232 device. It is assumed that if RAM is failing, the screen may not be readable and program execution will fail because there is no stack or system variables. The program will continue to test RAM and print errors, but no screen will be displayed (the screen may turn red). Repair RAM. If the keyboard fails, it will be inactivated. The user must connect a terminal to the RS232 port. The diagnostic program looks for keystrokes from the RS232 device. If the display is unreadable, the RS232 terminal should be used. All messages are printed to the RS232 port as well as the screen. 3.4.2 Power-Up Initialization Errors INITIALIZATION (Errors occurring before the title and menu appear.) I1 RAM data line is stuck. I2 RAM disturbance. Location is altered by write to another location. I3 RAM addressing. Wrong location is being addressed. I4 MMU error. No DTACK after RAM access. I5 RAM sizing error. Uppermost address fails. I6 Bus Error handling failed. Bus Error occurred (on purpose), but caused a crash (e.g. system was unable to read the vector from RAM). I7 Bus Error not detected. GSTMCU not asserting Bus Error or the signal is not reaching the 68000. T0 MFP timers failed. T1 Vertical sync timing failed. T2 Horizontal sync timing failed. T3 Display Enable Interrupt failed. T4 Memory Controller video address counter failed. T5 PSG Bus test. PSG chip is causing a bus error by staying on the data bus too long. T6 Floppy Disk Controller Bus test. FDC chip is causing a bus error by staying on the data bus too long. K0 Stuck key K1 Keyboard controller is not responding. K2 Keyboard controller reports error. 3.4.3 Test Menu The normal screen will be dark blue with white letters. The test title and revision number are displayed at the top, with the amount of RAM and keyboard controller revision below, and a test menu below that. To select tests, the user types the keys corresponding to those tests, and then the RETURN key. After the operator selects a test, the program will not proceed until the key break is detected (when the operator releases the key). This prevents false "stuck key" messages in the keyboard test. Many iterations of the test or tests chosen can be run by typing in the number of cycles just before typing RETURN. Typing a zero will cause the test sequence to run continuously. To stop a cycle before completion, hit the ESC key (there may be some delay in some tests before the test stops). As each cycle completes, the total numbers of cycles will be displayed on the screen. Several hidden key sequences are also provided. Main Menu: Mega-STer Field Service Diagnostic Test Rev. 1.3 c 1991, Atari Corp. 4M RAM Keyboard revision 2 60 Hz O.S. Version 2.02 USA NTSC R RAM Test O O.S. ROMs K Keyboard M MIDI S Serial Port T Timing D DMA Port I SCC L Real-Time Clock F Floppy Disk P Printer/Mouse/Joy Ports G short BLiT Y long BLiT V VME Q Run All Unattended Tests (R,O,K,M,S,T,D,I,L,F,P,Y,V) Z Run Unattended Internal tests (R,O,K,G,T,V,L) A Audio C Color H High resolution J Hard Disk Read/Write E Examine/Modify memory B Set RS232 rate X Toggle video output--50/60 Hz ? Help Enter Letter(s), and ReturnHidden Key Sequences: 1 System Clock 8 MHz cache off 2 System Clock 16 MHz cache off 3 System Clock 16 MHz cache on 5 8 MHz floppy clock set 6 16 MHz floppy clock set (1.44 Meg Drive) 7 Software Date The RAM size, keyboard revision, O.S. version, country (or language), and television standard (PAL or NTSC) are shown. The 'Q' selection sequences through all the tests except for Audio, Color, High resolution monitor, and Hard Disk Read/Write. The 'Z' selection sequences through RAM, ROM, Keyboard, short BLiT, Timing, VME, and Real-Time Clock. Selection 'E' enables the operator to examine or modify RAM or hardware registers. 'B' enables the operator to change the baud rate on the RS232 port. Pressing the up arrow increases it, pressing the down arrow decreases it. For example T M2 L3 V0 would result in the Timing test being run once, MIDI test twicw, Real-Time Clock test three times, and VME indefinitely or until the key is pressed. After a test or series of tests completes, the pass/fail status and error report, if any, will be displayed. When the selected test(s) have passed the screen will turn green accompanied by a short beep. If the selected test(s) fails the screen will turn red accompanied by an audible tone which oscillates. This allows the user to perform other troubleshooting functions while the running diagnostics without having to look directly at the screen for an indication of a Pass or Fail status. Press the space bar to return to the menu. If multiple tests are selected, the sequence can be halted before completion by pressing the ESC key. At the completion of the current test, the sequence will halt, with the options of either continuing or returning to the menu. In some cases there will be a considerable delay before the current test completes and the keystroke is detected.3.4.4 Summary of Tests 3.4.4.1 GENLOCK The GENLOCK switch position allows the system to synchronize the MegaSTer video with an external source. The system clock is also phase-locked to the input sync signal. To do this pin three of the monitor connector is grounded, and the external clock is sent to the system on pin 4. The GENLOCK test can be run using the INT/GENLOCK switch on the MegaSTer port test fixture. The GENLOCK test is run twice. Toggling the switch to the GENLOCK position on the STer test fixture should switch between the normal menu and no menu. With no menu a "sweeping" cycle should be heard. Reset the computer between each change of the INT/GENLOCK switch. NOTE: RUN THIS TEST ONLY WITH A COLOR MONITOR. 3.4.4.2 RAM Test (R) System RAM is tested in three stages: low 2 kbytes, middle (up to 64k), and from 64k to top. The test patterns used are: all ones, all zeros, a counting pattern (data=low word of the address), reverse counting pattern (data=complement of address low word). The counting pattern is copied from the top and bottom of a 32 Kbyte buffer into the current 32 Kbytes of video RAM, then shifts video RAM to a new area, verifies the pattern, and repeats the test, until the top of RAM is reached. Finally, addressing at 64k boundaries is checked by writing unique pattern in last 256 bytes of each 64k block. The cache RAM is also tested as well as a CAS1 test to detect opens and shorts on the CAS signal for the upper bank of memory. If an error occurs, the display turns red accompanied by an oscillating tone and the error code is displayed, followed by the address, data written, data read, and the bits which did not agree. For example: " R2 45603E W:603E R:613C bad bits: 1,8".In units having more than one bank the address as well as the bit position must be used to find the correct SIMM. The following table gives a correspondence between the addresses and banks for various models: One Megabyte Machines Address Bank Bad Bit(s) SIMM 0-07FFFF bank 0 1-8 U703 bank 0 9-16 U701 0080000-0FFFFF bank 1 1-8 U704 bank 1 9-16 U702 Two and Four Megabyte Machines Address Bank Bad Bit(s) SIMM 0-1FFFFF bank 0 1-8 U703 bank 0 9-16 U701 200000-3FFFFF bank 1 1-8 U704 bank 1 9-16 U702 A bank is 16 bits wide and consists of two 1Mbit X 8 SIMMS. RAM Error Codes Except where noted, repair by replacing the SIMM corresponding to the indicated bit(s). R0 Error in low memory, possibly affecting program execution. R1 Error in SIMM. R2 Address error. Bad SIMM or memory controller. Address line not working. R3 Address error at 64k boundary. R4 Error during video RAM test. Bad SIMM. Cache RAM Error during cache RAM test. Bad cache RAM chip. 3.4.4.3 ROM Test (O) This test reads the configuration bytes of the operating system to determine the version, language/country, and TV standard (PAL or NTSC). All bytes from operating system ROMs are then read and the checksums are calculated and displayed. A CRC is then calculated for each EPROM. The test fails if the CRC calculated does not match the CRC found in the last location in each EPROM (e.g. Version 2, French). Incorrect CRCs are indicated by the display turning red and an oscillating tone followed by a message. If an error is displayed, replace the corresponding ROM. 3.4.4.4 Color Test (C) This test verifies the Video Shifter. Seven color bands are displayed: red, green, blue, cyan, magenta, yellow, and white. Each band consists of 8 levels of intensity. All 16 color palettes are represented, each palette is a vertical strip across the screen (strips should not be discernable, but each color should be a straight line across the screen). Because of the tight timing involved, keystroke interrupts will cause the display to jitter. The operator should see that there are no gaps or missing scan lines in the display. If lines are missing, check the three outputs on the Video Shifter for that color, and verify the values of the resistors on the output. Too low a brightness setting on the monitor will cause the monitor not to distinguish between fine levels, making it appear there are only four levels being output. The Video Shifter has four outputs for red (R0,R1,R2,R3), green (G0,G1,G2,G3) and blue (B0,B1,B2,B3). Each of these outputs is summed together by a resistor network to give 8 levels of intensity for each color, depending on which of the outputs are on. The values of the resistors give different weight to each output. The value of the resistor at R0 is twice that of R1, which is twice that of R2. (Note: some versions have these resistors inside the shifter.) This allows us to get 8 equal steps on the summed outputs. For example, R0 on and R1 and R2 off = 1/8, R0 off, R1 and R2 on = 7/8. This signal then passes through a transistor amplifier, and from there to the video monitor connector. NOTE: this resistor network is incorporated into the gate array chip in later versions. Symptoms and fixes: Missing primary color. Check the output of the transistor amplifier. Q503 is blue, Q502 is green, Q501 is red. Look for a staircase pattern (eight levels of intensity). If the signal is there, trace forward to the video connector, if not, trace backward to the Video Shifter, until the faulty component is found. Primary colors present, secondaries missing or incorrect. Replace the Video Shifter (U502). Coarse change in intensity (not a smooth dark to light transition). Replace Video Shifter (U502) or look for a short on the output of one of the three color outputs for the appropriate color. Specks or lines on the screen. This can be caused by bad RAM; if RAM has been tested and is good, replace the Video Shifter (U502). Wavering display, horizontal lines not occurring in the same place every time. The processor may be getting extra interrupts (if the processor is required to handle additional interrupts, it will not have time to change all color registers during a horizontal scan time). Examine the MFP interrupt request (pin 32). There should be an interrupt every 126 microseconds (2 display lines) from Display Enable (pin 20). If additional interrupts occur, locate the source: the inputs at pins 22-29 should all be high. If no external (to the MFP) source for the interrupts is found, replace the MFP (U306). NOTE: if the keyboard is not connected, the input to the 6850 will be low, causing continual interrupts. 3.4.4.5 Keyboard Test (K) Two types of test are run. The keyboard self-test is done first, and if this passes, a screen is displayed representing the keyboard. The operator presses keys and observes that the corresponding character on the screen changes (reverses background color). The key will also be displayed in the lower half of the screen. The mouse buttons and four directions are also shown on the screen. Connect the mouse and move in any direction and the arrow will flicker. Any key clicks while the mouse is moving indicates a short. NOTE: it is possible, if pressing keys very rapidly, to leave the representation of the key on screen in a depressed state. This does not indicate a problem with the hardware. The self-test checks communication between the CPU and the keyboard microcomputer, and checks RAM and ROM in the keyboard microcomputer, and scans the keyboard for stuck keys. Keyboard Error Codes K0 Stuck key. A key closure was detected while the keyboard self test was executing. K1 Keyboard not responding. A command was sent to the keyboard processor and no status was returned within the allowed time. The keyboard needs to be replaced or the communication channel through the 6850 (U304) is not functional. K2 Keyboard status error. The self test command was sent to the keyboard, on completion of the test, the keyboard sent an error status. Replace the keyboard. 3.4.4.6 MIDI Tests (M) This test sends data out the MIDI port, (data loops back through the cable) and reads from the input and verifies the data is correct. This also tests the interrupt from the 6850 through the MFP chip. The LED in the loopback cable will blink as data is sent (not all cables have the LED). MIDI Error Codes M0 Data not received. Trace the signal from the output of the 6850 (U303), through the drivers (U301), loopback cable, and receivers to the input of the 6850 (U303). Replace the defective component. M1 Write/Read data mismatch. The data written was not the same as the data read. Replace 6850 (U303). M2 Input frame error. Bad 6850 (U303) or bad driver (U301) or receiver causing noisy signal. M3 Input parity error. Bad 6850 (U303) or bad driver (U301) or receiver causing noisy signal. M4 Input data overrun. The 6850 received a byte before the previous byte was read. Probable bad 6850 (U303), also can be caused by the MFP (U306) not responding to the interrupt request. 3.4.4.7 Serial Port Tests (S) NOTE: DO NOT INSTALL THE RS232 LOOPBACK CONNECTORS UNTIL AFTER THE MAIN MENU IS DISPLAYED. First the RS232 control lines are tested (which are tied together by the loopback connector), then the data loopback is tested. Data is checked transmitting/receiving using a polling method first, then using interrupts. Data is transmitted at 300, 600, 1200...19200 bps. Data transmission is performed by the MFP and the 1488 and 1489 driver and receiver chips (U310, U311). Interrupts are a function of the MFP (U306). Control lines are output by the PSG chip (U305) and input on the MFP. Note that this test does not thoroughly test the drive capability of the port. If the test passes, but the unit fails in use, it is likely that the 1488 (U311) or 1489 (U310) chips are bad. Serial Port Error Codes Data transmission error: S0 Data not received. Check signal path: MFP (U306) pin 9 to 1488 (U311) pin 5 to J305 pin 3 to J305 pin 2 to 1489 (U310) pin 1 to MFP (U306) pin 10. S1 Data mismatch. Data read was not what was sent. Check integrity of the signal. May be bad driver (U311), receiver (U310), or MFP (U306). S2 Input frame error. Incorrect time between start and stop bits. Probable MFP failure (U306). S3 Input parity error. Input data had incorrect parity. Probable MFP failure (U306). S4 Input data overrun. A byte was received before the CPU read the previous byte. MFP failure (U306) or, less likely, GSTMCU (U501) failure. S5 No IRQ. CPU did not detect an interrupt by the MFP. MFP (U306) or GSTMCU (U501) failure. S6 Transmit error. MFP (U306) transmitter failed. SERIAL PORT ERROR CODES (C0ntinued) S7 Transmit error interrupt. An error condition was created intentionally to cause an interrupt, and the MFP did not respond. S8 Receive error interrupt. An error condition was created intentionally to cause an interrupt, and the MFP did not respond. S9 RI/DTR connection. Signal sent at DTR is not detected at RI. SA DCD/DTR connection. Signal sent at DTR is not detected at DCD. SB RTS/CTS connection. Signal sent at RTS is not detected at CTS. SC RS232 input shorted to output. The input and outputs of the MFP serial port are shorted together. 3.4.4.8 SCC Test (I) The SCC diagnostic tests the SCC chip for several functions. Internal loopback polled (asynch), break (test ext loopback), external loopback polled (asynch), modem control lines, and external loopback interrupt (asynch). Ports A and B are tested in RS232 mode, and the LAN at port A is also tested. SCC Error Codes Port A Errors: SCC A internal loopback: Transmitter time-out Transmitter failed. SCC A internal loopback: Receiver time-out Receiver failed. SCC A internal loopback: Overrun A byte was received before the CPU read the previous byte. SCC A internal loopback: Framing error Incorrect time between start and stop bits. SCC A internal loopback: Parity error Input data had incorrect parity. SCC A internal loopback: Data compare Data read was not what was sent. Port A has no loopback connector The loopback connector is not installed on Port A. LAN has no loopback connector The loopback connector is not installed on the LAN Port. LAN ERROR: DCD IS ACTIVE WITHOUT RTS ON The Carrier detect signal is active without a request to send. LAN ERROR: RTS IS ACTIVE BUT DCD IS NOT RESPONDING The request to send signal is on but no carrier is active. Port A async mode: Transmitter time-out Transmitter failed. Port A async mode: Receiver time-out Receiver failed. Port A async mode: Overrun A byte was received before the CPU read the previous byte. Port A async mode: Framing error Incorrect time between start and stop bits. Port A async mode: Parity error Input data had incorrect parity. Port A async mode: Data compare Data read was not what was sent. Port A modem control error: DTR-DCD Signal sent at DTR is not detected at DCD. Port A modem control error: DTR-DSR Signal sent at DTR is not detected at DSR. Port A modem control error: RTS-CTS Signal sent at RTS is not detected at CTS. Port B Errors: SCC B internal loopback: Transmitter time-out Transmitter failed. SCC B internal loopback: Receiver time-out Receiver failed. SCC B internal loopback: Overrun A byte was received before the CPU read the previous byte. SCC B internal loopback: Framing error Incorrect time between start and stop bits. SCC B internal loopback: Parity error Input data had incorrect parity. SCC B internal loopback: Data compare Data read was not what was sent. Port B has no loopback connector The loopback connector is not installed on Port B. Port B async mode: Transmitter time-out Transmitter failed. Port B async mode: Receiver time-out Receiver failed. Port B async mode: Overrun A byte was received before the CPU read the previous byte. Port B async mode: Framing error Incorrect time between start and stop bits. Port B async mode: Parity error Input data had incorrect parity. Port B async mode: Data compare Data read was not what was sent. Port B modem control error: DTR-DCD Signal sent at DTR is not detected at DCD. Port B modem control error: DTR-DSR Signal sent at DTR is not detected at DSR. Port B modem control error: RTS-CTS Signal sent at RTS is not detected at CTS. SCC Interrupt Errors: SCC interrupt error: Transmitter time-out Transmitter failed. SCC interrupt error: Receiver time-out Receiver failed. SCC interrupt error: Overrun A byte was received before the CPU read the previous byte. SCC interrupt error: Framing error Incorrect time between start and stop bits. SCC interrupt error: Parity error Input data had incorrect parity. SCC interrupt error: Data compare Data read was not what was sent. No Tx interrupt A transmit command was issued but no interrupt occurred. No Rx interrupt A receive command was issued but no interrupt occurred. 3.4.4.9 Audio Test (A) This test requires the operator to decide subjectively if the test passes or fails. PSG Sound A sound is output on each of the three sound generator channels. The 5/8 sound is a sweep from low to high frequency. Verify that the sound can be heard throughout the range with no drop in audio level. DMA Sound Connect an oscilloscope at the stereo output jacks. Set the oscilloscope to 1 ms/division and 5 volts/division. There are four parts to this test. After observing the signals in each part of the test, proceed to the next part of the test by pressing the space bar. In each case the output signal amplitude should go from 0 volts to maximum amplitude in steps. The four parts of this test are as follows: a. Mono 1 kHz. Both channels will output the same signal which should approximate a sine wave of 5-6 volts in amplitude. b. Stereo 1 kHz/500 kHz. Verify that the right and left channels have the correct frequency. As one channel increases in amplitude, the other channel decreases. Maximum amplitude is 5-6 volts. c. Treble. A 12.5 kHz signal is output on both channels. Maximum amplitude is about 6 volts. d. Bass. a 50 kHz is output on both channels. Maximum amplitude is about 6 volts. 3.4.4.10 Timing Tests (T) These tests are run at power-up as well as being selectable from the menu. The MFP timers, the GSTMCU timing for VSYNC and HSYNC, and video display counters are tested. The video display test redirects display memory throughout RAM and verifies that the correct addresses are generated. Odd patterns may flash on screen as this test is run. There are two tests which check the bus timing for the Floppy Disk Controller and PSG chips. An error message is printed to the screen, then the test is run. If the test passes, the message is erased. If not, a Bus Error will occur and the message will remain. If a terminal is connected to the RS232 port, the message will not be erased, but "Pass" will be printed. Timing Test Error Codes T0 MFP timer error. One or more of the four timers in the MFP (U306) did not generate an interrupt on counting down . T1 Vertical Sync. GSTMCU (U501) is not generating vertical sync in the required time period. T2 Horizontal Sync. GSTMCU (U501) is not generating horizontal sync in the required time period. T3 Display Enable. GSTMCU (U501) is not generating DE output or the MFP (U306) is not generating an interrupt. T4 Video Counter in Memory Controller. The GSTMCU chip (U501) is not generating the correct addresses for the display. This will result in a broken-up display in some or all display modes. T5 PSG Bus Test. The PSG chip (U305) is defective. T6 1772 Bus Test. The Floppy Disk Controller chip (U405) is defective. 3.4.4.11 DMA Tests (D) Four sectors (2048 bytes) of data are written to the RAM on the port test fixture via high speed DMA, then read back and verified. This test is repeated many times for RAM addresses throughout the range of RAM.DMA Test Error Codes D0 DMA time-out. No DMA occurred due to faulty DMA Controller (U404), GSTMCU (U501), or the HDINT interrupt was not processed by the MFP (U306). The failure can be isolated by seeing if the DMA Controller responds to HDRQ from the test fixture with ACK. Verify the MFP by seeing that the HDINT input causes an INTR output from the MFP. D1 DMA count error. the number of bytes transferred was incorrect. The GSTMCU chip (U501) or DMA Controller (U404) is bad. D2 Data data mismatch. The data received from the DMA port was not the same as the data sent. Replace the DMA Controller (U404). If the problem persists, check the data lines to the port for opens and shorts. A third possibility is that a defective Floppy Disk Controller (U405) is loading the bus. D3 DMA not responding. Replace the DMA Controller (U404). 3.4.4.12 Floppy Disk Tests (F) In single test mode, a menu is displayed showing seven options: Quick test. For each disk installed, formats, writes, and reads tracks 0, 1, and 79 of side 0. If double sided, formats and writes track 79 of side 1 and verifies that side 0 was not overwritten. If no disks are installed, checks to see what drives are on-line and if they are double or single sided. To assure that the drives are correctly tested, the operator should install (menu option 6) before calling the test. Once the test is run, the drives become installed, and will be displayed on the menu screen (below the RAM size). Read Alignment Disk. Continuously reads a track, for checking alignment with an analog alignment diskette. The track to be read may be input by the operator. If "Return" is pressed without entering a number, the default is track 40. Disk Interchange Test. Checks to see if diskettes from two disk drives each can be read by the other disk drive. Disk Exerciser. A more thorough disk test; tests all sectors on the disk for an indefinite period of time.Check copy protect tracks (80-82). Tests tracks 80-82, which are used by some software companies for copy protection. Not all manufacturers disk drives will write these tracks. NOTE: this test is for information only and should not be used to reject a mechanism. Test Speed. The rotational speed of the drive is tested and displayed on the screen as the period of rotation. The acceptable range is 196-204 milliseconds. The highest and lowest values measured are displayed. The test stops when any key is pressed. Install disk drives. Specify how many and what type of disks to test. One additional test which can be performed is testing the write protect detection. Slide the write protect tab to the protected position, and run test #1. You should see "F5 Write protected" displayed if the drive has been installed, or "Unable to write disk" displayed if the drive has not been installed. If more than one test is selected from the main menu, the floppy menu will not appear, but the Quick Test will be selected automatically. Floppy Test Error Codes No floppies connected The controller cannot read index pulses. The cable may be improperly connected, or the drive has no power, or the drive is faulty. F0 Drive not selected. Drive was installed, but failed attempting restore (seek to track 0). Check connection of cables, power to drive. Verify the light on the front of the drive goes on. Listen for the sound of the head seeking (the slide on the diskette should open). If all this occurs, TR0 (pin 23 on the Floppy Disk Controller U405) should go low. If so, check for an interrupt on pin 28 of the Floppy Disk Controller. If none, replace the Floppy Disk Controller (U405). Else trace the interrupt to the MFP (U306), verify that the MFP responds by asserting INTR. If the drive is not being selected (no light), check the PSG chip (U305). Pin 20 should go low when drive A is selected, and pin 19 should go low when drive B is selected. If not, replace the PSG (U305).Error Writing (Formerly F1) Error Reading (Formerly F2) Error Formatting (Formerly F3) Displays a more specific error message along with the above message such as F9 CRC error". F4 Seek error. Verify that the STEP, MO, and DIRC outputs from the Floppy Disk Controller are sent to the drive. Probable failure in the Floppy Disk Controller (U405), but the drive is also suspect. F5 Write protected. Check the write protect tab on the diskette. If OK, verify that the WP input (Floppy Disk Controller U405 pin 25) is going low during the test; if it is, then the Floppy Disk Controller is defective; if not, the problem is with the disk drive. F6 Read compare error. Data read from the disk was not what was supposed to be written. Check in the following order: diskette, disk drive, Floppy Disk Controller (U405), and DMA Controller (U404). F7 DMA error. DMA Controller could not respond to a request for DMA. Replace the DMA Controller (U404). If error persists, check FDRQ while running the test. It should normally be low and go high with each data byte transferred. If stuck high, push the reset button and verify that MR (Floppy Disk Controller U405 pin 13) goes low. If not, trace RESET to its source. If MR is OK, but FDRQ is still stuck, replace the Floppy Disk Controller (U405). F8 DMA count error. Replace the GSTMCU (U501), if that does not fix it, replace the DMA Controller (U404). F9 CRC error. The diskette or disk drive may be bad, else replace the Floppy Disk Controller (U405). FA Record not found. The Floppy Disk Controller could not read a sector header. May be a bad diskette, drive or Floppy Disk Controller (U405). If the test fails drive A but not drive B, the Floppy Disk Controller is not at fault (likewise fails B not A). FB Lost data. Data was transferred to the Floppy Disk Controller faster than the Floppy Disk Controller could transfer to the DMA Controller. If DMA Port test passes, the Floppy Disk Controller is probably bad (U405). The DMA Controller (U404) could also be at fault. FC Side select error - single sided drive. The test tried to write both sides of the diskette, but writing side 1 caused side 0 to be overwritten. FD Drive not ready. The format/write/read operation timed-out. Probably a bad disk drive. Verify by checking another drive. Could also be a faulty Floppy Disk Controller (U405). 3.4.4.13 Printer and Joystick Port Tests (P) The port test fixture is used to test the parallel printer port and joystick ports. The parallel port test writes to a latch on the test fixture and reads back data. The joystick port test outputs data on the parallel port, which is directed through the test fixture to the joystick ports. The keyboard reads the joystick data in response to commands from the CPU. The cables connecting the joystick ports to the test fixture must not be reversed, or the printer and joystick tests will fail. Printer/Joystick Error Codes P0 Printer port error. Data read from the printer port was not what was written. Verify that the data lines on the PSG chip (U305 pins 6-13) are toggling when the test is run. If not, run the RS232 test. If the RI-DTR and DCD-DTR errors occur, the chip is probably not being selected. Check if the chip selects are being activated and the 2MHz clock is present. If the PSG is selected and not outputting signals, replace it (U305). If the data lines toggle, verify continuity. Also verify that J11 (Joystick 0) pin 3 is pulled up. Verify the test fixture is good by testing another computer. If it is OK, replace the PSG (U305). P1 Busy input error. The input to the MFP is not being read, or the STROBE output from the PSG is not functioning, or Joystick 0 pin 3 is not connected. If the P0 error also occurs, see handling for that. Otherwise, look for a signal arriving at MFP (U306) pin 25 from J304 pin 11. If no signal at J5, the test fixture may be bad. Verify with another computer. J0 Joystick Port 0. The keyboard input is not functioning. If the Busy input error occurs, fix that first. Otherwise, replace the keyboard. If error persists, check continuity from J11 pins 1,2,3,4 to J12 pins 12,10,9,8 respectively. J1 Joystick Port 1. The keyboard input is not functioning. If the Busy input error occurs, fix that first. Otherwise, replace the keyboard. If error persists, check continuity from J11 pins 1,2,3,4 to J12 pins 7,5,4,3 respectively. J2 Joystick time-out. Joystick inputs were simulated by outputting data on the printer port and routing it via the test fixture to the joystick ports. Joystick inputs are detected by the keyboard and sent to the CPU via the 6850. This error can be caused by printer port failure (code P0), keyboard failure, keyboard-CPU communication line, or a faulty test fixture. If the power-up keyboard test passes, this eliminates any problem with keyboard-CPU communication. J3 Left button input. If P1 error occurs, fix that first. Otherwise replace the keyboard. J4 Right button input. If P1 error occurs, fix that first. Otherwise replace the keyboard. 3.4.4.14 High Resolution Monitor (H) If this test is selected while a color monitor is connected, a message is displayed to connect the monochrome monitor. The CPU waits for an interrupt from the MONOMON input to the MFP, and when received (the operator connects the monochrome monitor), changes the display to high resolution. The display screen shows horizontal and vertical lines, each 2 pixels in width. The screen will reverse every two seconds. When the operator sees the display is correct, he unplugs the monochrome monitor and re-connects the RGB monitor and the display should return to normal. 3.4.4.15 Graphics Chip (BLiT) (G,Y) Two tests are available for this chip. The "short BLiT tests the ability of the blitter to move blocks of memory around and perform logical operations on the data. No patterns appear on the screen. If an error is detected, one of the error codes (G1-G12) is displayed. In the "long BLiT test", a triangle is drawn on the screen and rotated 180 degrees until a rectangle is formed. If a color monitor is used, two identical images will be drawn. If an error occurs, the error code G14 will be displayed. Corrective action for any error is the same: 1) verify the jumpers for the BLiT chip are installed correctly, 2) replace the chip (U205). Graphics Chip Error Codes G1 halftone RAM (internal RAM in BLiT chip) G2 endmask G3 operation G4 halftone op G5 skew G6 reverse blt G7 force extra source read G8 smudge G9 x count G10 y count G11 time-out G12 address count G13 Blitter Bus Error 3.4.4.16 Real-Time Clock (L) The test saves the current time and date, and writes a new time, waits one second, and verifies that hours, minutes, seconds, etc. have all rolled over. This procedure is repeated for another date to verify all registers.3.4.4.17 VME Connector (V) This test is performed in two parts. The test is designed to check the bus connected to VME option cards, not the VME cards themselves. One part of the test requires that a XYCOM 4-port serial adapter be installed. The test is run and then the system is powered down and the board removed. The other part of the test requires that a Greenspring VME memory card be installed. The switches on the card must be set to 2 and 4 off and the rest on. The system is then powered up and the VME test run again. Failures during this test are most likely to show up as bad address or data errors. 3.4.4.18 Hard Disk Read/Write (J) This tests the hard disk interface by writing and reading one complete track of the hard disk. It is not intended to test the hard disk drive. It does test the computer DMA circuitry. The test has been found to be more effective than the DMA test for some types of failures. These failures normally show up as "Data Compare" errors. The test program will save the data on the cylinder used for testing and restore the data when the test is complete. (Quit or Park Heads is selected). The test will run until the operator presses the ESC key. There is no pass condition. A failure will normally show up within a few seconds if it is going to occur. Hard Disk Read/Write Error Messages Controller Not Responding. This means there is no communication between the system and the hard disk. Cycling power on the hard disk may correct this condition. Operation Timed Out. The system sent a command which was accepted by the hard disk. The hard disk did not return a completion code in time. Command Error. The hard disk attempted to execute a command but an error in the hard disk occurred. DMA Count Error. After completing a data transfer the byte count of the data in system memory did not match the number of bytes sent. Data Compare Error. The data written to the hard disk and then read back did not match.3.5 ERROR CODES QUICK REFERENCE This is a brief summary of all error code which may occur when running the diagnostic. Initialization (Errors occurring before the title and menu appear.) I1 RAM data line is stuck. I2 RAM disturbance. Location is altered by write to another location. I3 RAM addressing. Wrong location is being addressed. I4 MMU error. No DTACK after RAM access. I5 RAM sizing error. Uppermost address fails. I6 Bus Error handling failed. Bus Error occurred (on purpose), but caused a crash (e.g. system was unable to read the vector from RAM). I7 Bus Error not detected. GSTMCU not asserting Bus Error or the signal is not reaching the 68000. Exceptions (may occur at any time) E1-E5 not used E6 Autovector error. IPL0 is grounded or 68000 is bad. E7 Spurious interrupt. Bus error during exception processing. Device interrupted, but did not provide interrupt vector. E8 Internal Exception (generated by 68000). E9 Bad Instruction Fetch. EA Address error. Tried to read an instruction from an odd address or read or write word or long word at an odd address. Usually this error is preceded by a bus error or bad instruction fetch.EB Bus error. Generated internally by the 68000 or externally by GSTMCU. Usually caused by device not responding. Displays the address of the device being accessed. RAM R0 Error in low memory, possibly affecting program execution. R1 Error in RAM chip. R2 Address error. Bad RAM chip or memory controller. Address line not working. R3 Address error at 64k boundary. R4 Error during video RAM test. Bad RAM chip. Cache RAM Cache RAM failure. Keyboard K0 Stuck key K1 Keyboard controller is not responding. K2 Keyboard controller reports error. MIDI M0 Data not received. M1 Data received is not what was sent. M2 Data input framing error. M3 Parity error. M4 Data overrun. Byte was not read from the 6850 before next byte arrived.RS232 S0 Data not received. S1 Data received is not what was sent. S2 Data input framing error. S3 Parity error. S4 Data overrun. Byte was not read from the MFP before the next byte arrived. S5 IRQ. The MFP is not generating interrupts for transmit or receive. S6 Transmitter error - MFP. S7 No interrupt from transmit error (MFP). S8 No interrupt from receive error (MFP). S9 DTR - RI. These signals are connected by the loopback connector. Changing DTR does not cause change in RI. SA DTR - DCD. Same as S9 for these signals. SB RTS - CTS. Same as S9 for these signals. SC RS232 input shorted to output. The input and outputs of the MFP serial port are shorted together. SCC Error Codes Port A Errors: SCC A internal loopback: Transmitter time-out Transmitter failed. SCC A internal loopback: Receiver time-out Receiver failed. SCC A internal loopback: Overrun A byte was received before the CPU read the previous byte. SCC A internal loopback: Framing error Incorrect time between start and stop bits. SCC A internal loopback: Parity error Input data had incorrect parity. SCC A internal loopback: Data compare Data read was not what was sent. Port A has no loopback connector The loopback connector is not installed on Port A. LAN has no loopback connector The loopback connector is not installed on the LAN Port. LAN ERROR: DCD IS ACTIVE WITHOUT RTS ON The Carrier detect signal is active without a request to send. LAN ERROR: RTS IS ACTIVE BUT DCD IS NOT RESPONDING The request to send signal is on but no carrier is active. Port A async mode: Transmitter time-out Transmitter failed. Port A async mode: Receiver time-out Receiver failed. Port A async mode: Overrun A byte was received before the CPU read the previous byte. Port A async mode: Framing error Incorrect time between start and stop bits. Port A async mode: Parity error Input data had incorrect parity. Port A async mode: Data compare Data read was not what was sent. Port A modem control error: DTR-DCD Signal sent at DTR is not detected at DCD. Port A modem control error: DTR-DSR Signal sent at DTR is not detected at DSR. Port A modem control error: RTS-CTS Signal sent at RTS is not detected at CTS. Port B Errors: SCC B internal loopback: Transmitter time-out Transmitter failed. SCC B internal loopback: Receiver time-out Receiver failed. SCC B internal loopback: Overrun A byte was received before the CPU read the previous byte. SCC B internal loopback: Framing error Incorrect time between start and stop bits. SCC B internal loopback: Parity error Input data had incorrect parity. SCC B internal loopback: Data compare Data read was not what was sent. Port B has no loopback connector The loopback connector is not installed on Port B. Port B async mode: Transmitter time-out Transmitter failed. Port B async mode: Receiver time-out Receiver failed. Port B async mode: Overrun A byte was received before the CPU read the previous byte. Port B async mode: Framing error Incorrect time between start and stop bits. Port B async mode: Parity error Input data had incorrect parity. Port B async mode: Data compare Data read was not what was sent. Port B modem control error: DTR-DCD Signal sent at DTR is not detected at DCD. Port B modem control error: DTR-DSR Signal sent at DTR is not detected at DSR. Port B modem control error: RTS-CTS Signal sent at RTS is not detected at CTS. SCC Interrupt Errors: SCC interrupt error: Transmitter time-out Transmitter failed. SCC interrupt error: Receiver time-out Receiver failed. SCC interrupt error: Overrun A byte was received before the CPU read the previous byte. SCC interrupt error: Framing error Incorrect time between start and stop bits. SCC interrupt error: Parity error Input data had incorrect parity. SCC interrupt error: Data compare Data read was not what was sent. No Tx interrupt A transmit command was issued but no interrupt occurred. No Rx interrupt A receive command was issued but no interrupt occurred. DMA D0 Time-out. DMA did not take place, or interrupt not detected. D1 DMA count error. Not all bytes arrived. Possible Memory Controller or GSTMCU error. D3 DMA Controller not responding. Timing T0 MFP timers failed. T1 Vertical sync timing failed. T2 Horizontal sync timing failed. T3 Display Enable Interrupt failed. T4 Memory Controller video address counter failed. T5 PSG Bus test. PSG chip is causing a bus error by staying on the data bus too long. T6 Floppy Disk Controller Bus test. Floppy Disk Controller chip is causing a bus error by staying on the data bus too long. Printer and Joystick Ports P0 Printer port error. P1 Busy (printer port input) failed. J0 Joystick port 0 failed. J1 Joystick port 1 failed. J2 Joystick (keyboard controller) timed-out. J3 Left button line failed. J4 Right button line failed. Floppy Disk Drive F0 Drive off-line. Not responding to restore (seek track 0). Former F1, F2, and F3 write and read errors are deleted. The message now will say "error writing" [or reading] and display the specific error found.) F4 Seek error. F5 Write protected. F6 Data compare. (Data read not equal to data written.) F7 DMA error. F8 DMA count error (Memory Controller counter.) F9 CRC error. FA Record not found. FB Lost data. FC Side select error. FD Drive not ready. Timed-out performing the command. BLiT G1 halftone RAM (internal RAM in BLiT chip) G2 endmask G3 operation G4 halftone op G5 skew G6 reverse blt G7 force extra source read G8 smudge G9 x count G10 y count G11 time-out G12 address count G13 Blitter Bus Error Real-Time Clock C0 no real-time clock C1 increment errorSECTION FOUR DISASSEMBLY/ASSEMBLY 4.1 MegaSTer DISASSEMBLY Use the following procedure to disassemble the MegaSTer. Refer to Assembly Drawing, Section 7. Top Cover Removal: Turn off your computer and disconnect all cables from the sides and back of the unit (for example keyboard, power cord, external disk drive, and so on.). Turn your computer over and place it on its top. Remove the ten (10) screws located in the square holes on the bottom cover. With a slotted screwdriver loosen the retaining screw holding the accessory cover in place. While holding the computer's top cover and base together and holding the accessory cover in place turn the unit back over and set it on the bottom. Lift up the front of the accessory cover and remove it from the computer. If a hard disk is present, set the hard disk on its side on the top cover. Disconnect the power and interface cables from the hard disk. Set the accessory cover aside. Lift off the top cover and set it on its back behind the bottom case. Be sure to take care with the cables attached to the floppy disk drive and the power LED cable. Disconnect the power, interface, and LED cables from the floppy drive. Set the top cover aside. Floppy Disk Removal: Remove the top cover. Remove the 4 screws holding the floppy drive to the top cover. Remove the 4 screws holding the floppy disk to the mounting plate. Hard Disk Removal: Turn off your computer and disconnect all cables from the sides and back of the unit (for example keyboard, power cord, external disk drive, and so on.). Turn your computer over and place it on its top. With a slotted screwdriver loosen the retaining screw holding the accessory cover in place. While holding the computer's top cover and base together and holding the accessory cover in place turn the unit back over and set it on the bottom. Lift up the front of the accessory cover and set the hard disk on its side on the top cover. Disconnect the power and interface cables from the hard disk. Set the accessory cover aside. Power Supply Removal: Remove the top cover. Disconnect the power supply cables from the floppy disk drive and the hard disk drive if the hard disk is present. Remove the two (2) screws holding the power supply in place and set them aside. Remove the power supply and set it aside. Hard Disk Controller Board Removal: Locate the hard disk controller board on the main PCB. Also locate the mounting screw attached to the standoff on the main PCB. Disconnect the hard disk cable from the hard disk connector on the hard disk controller board. Unfasten the hard disk controller board from the standoff on the main PCB using by removing the mounting screw. Gently remove the hard disk controller board from the hard disk controller connector n the main PCB. Main PCB Removal: Remove the top cover and set it aside. Remove the three (3) screws from the main PCB and set them aside. Remove the power supply and set it aside. Remove the two (2) screws holding in any VME or serial connectors that are plugged into the VME slot and set them aside. Unplug the cable from the port serial board attached to the main printed circuit board. Remove the board from the VME slot. Remove the reset button cap from the plunger on the reset switch. Remove the main PCB.4.2 MegaSTer RE-ASSEMBLY Main PCB: Replace the main PCB. Replace the board from the VME slot. Replace the reset button cap from the plunger on the reset switch. Replace the two (2) screws holding in any VME or serial connectors that were plugged into the VME slot. Plug the cable from the serial board back into the main printed circuit board. Replace the three (3) screws from the main PCB. Power Supply: Replace the power supply. Replace the two (2) screws holding the power supply in place. Reconnect the power supply cables from the floppy disk drive and the hard disk drive if the hard disk is present. Hard Disk Controller Board Install the hard disk controller board by lining up the hard disk controller connector on the main PCB with the main PCB connector on the hard disk controller board. The standoff and the standoff hole should also be lined up. Gently push the hard disk controller board partially onto the hard disk controller connector on the main PCB. Make sure the connector pins of the main PCB connector are lined up with the socket connector on the hard disk controller board. Now push firmly down on the hard disk controller board until the connectors are fully engaged. Fasten the hard disk controller board to the standoff on the main PCB using the mounting screw with the washer. Reconnect the hard disk cable from the hard disk connector on the hard disk controller board. Floppy Disk: Replace the 4 screws holding the floppy disk to the mounting plate. Replace the 4 screws holding the floppy drive to the top cover. Top Cover: Set the top cover behind the base. Reconnect the power, interface, and LED cables from the floppy drive. Lift the top cover and set it back on the bottom case. Be sure to take care with the cables attached to the floppy disk drive, hard disk drive, and the power LED cable. Install the back of the accessory cover to the accessory cover opening. Make sure the tabs on the back of the accessory cover line up with the slots in the accessory cover opening. While holding the computer's top cover and base together and holding the accessory cover in place turn the unit over and set it on its top. Replace the ten (10) screws located in the square holes on the bottom cover. With a slotted screwdriver tighten the retaining screw holding the accessory cover in place. Hard Disk: Lift up the front of the accessory cover and set the hard disk on its side on the top cover. Disconnect the power and interface cables from the hard disk. Set the accessory cover aside. While holding the computer's top cover and base together and holding the accessory cover in place turn the unit back over and set it on the bottom. With a slotted screwdriver loosen the retaining screw holding the accessory cover in place. Turn your computer over and place it on its top.SECTION FIVE SYMPTOM CHECKLIST This section gives a brief summary of common problems and their most probable causes. For more detail, refer to the section on troubleshooting in this document, or the Diagnostic Cartridge Troubleshooting Guide. DISPLAY PROBLEMS: SYMPTOM PROBABLE CAUSE Black screen No power (check power supply), bad GSTMCU chip (U501), bad Video Shifter (U502). See TESTING section, "Troubleshooting a Dead Unit". White screen Video Shifter (U502), GSTMCU (U501), DMA Controller (U404), 68000 (U007). Use diagnostic cartridge with terminal connected via RS232 port. Dots/bars on screen RAM, GSTMCU chip (U501), Video Shifter (U502). Use diagnostic cartridge. One color missing Check signals at video connector pins 3, 6, and 10. Check video cable, Video summer, buffer, Video Shifter (U502). Check signals with oscilloscope. Monochrome Monitor Fails to Sync but Color Monitor Does Verify monochrome monitor detect bit is not open when monochrome monitor is connected. Check connection at J501, check MFP (U306) pin 32, replace MFP. Scrambled screen GSTMCU chip (U501). Use diagnostic cartridge. T.V. output bad Modulator (U503), phase locked loop. Trace signal with oscilloscope. DISK DRIVE PROBLEMS SYMPTOM PROBABLE CAUSE Disk won't boot Power supply, Floppy disk controller (U405), DMA Controller (U404), PSG chip (U305), disk drive. See if select light goes on, if not, check PSG outputs. Listen for motor spinning. If not, check power supply. Swap disk drive or try external drive. If not working, check DMA Controller (U404), Floppy disk controller (U405) with diagnostic cart. Disk won't format Floppy disk controller (U405), DMA Controller (U404), disk drive. System crash after loading files Diskette, disk drive, Floppy disk controller (U405), DMA (U404), or GSTMCU (U501). Swap diskette, retry. Use diagnostic cartridge to check Floppy disk controller, DMA Controller, GSTMCU, replace disk drive. KEYBOARD PROBLEMS: Bad keyboard, 6850 (U304), MFP (U306). MIDI PROBLEMS: Bad opto-isolator chip, 6850 (U303), inverter (U301). RS232 PROBLEMS: Bad MFP (U306), receiver (U310), driver (U311), or PSG chip (U305), power supply. PRINTER PORT PROBLEMS : Bad PSG (U305), MFP (U306) chips. HARD DISK PORT PROBLEMS: Bad DMA Controller (U404), GSTMCU (U501), Floppy disk controller ( U405 loading the bus).SECTION SIX DIAGNOSTIC FLOWCHARTS No Error on Diagnostic No Display No Monitor No TerminalNo Display No ErrorSECTION SEVEN PARTS LIST AND ASSEMBLY DRAWINGS MAJOR SUBASSEMBLIES MAIN PCB ASSEMBLIES 1 MEGABYTE MEMORY--WITHOUT COPROCESSOR ITEM PART NUMBER DESCRIPTION 9 CA400677-101 ASSY PCB MEGA STE/1 W/M USA 9 CA400677-102 ASSY PCB MEGA STE/1 W/M CAN 9 CA400677-103 ASSY PCB MEGA STE/1 W/M UK 9 CA400677-105 ASSY PCB MEGA STE/1 W/M GER 9 CA400677-106 ASSY PCB MEGA STE/1 W/M ITA 9 CA400677-107 ASSY PCB MEGA STE/1 W/H NET-UK 9 CA400677-108 ASSY PCB MEGA STE/1W/M NET-FRA 9 CA400677-109 ASSY PCB MEGA STE/1 W/H SPA 9 CA400677-110 ASSY PCB MEGA STE/1 W/M SWG 9 CA400677-111 ASSY PCB MEGA STE/1 W/M MEXICO 9 CA400677-112 ASSY PCB MEGA STE/1 W/M SWD 9 CA400677-114 ASSY PCB MEGA STE/1 W/M AUS 9 CA400677-120 ASSY PCB MEGA STE/1 W/M SWF 9 CA400677-104 ASSY PCB MEGA STE/1PERITEL FRA 1 MEGABYTE MEMORY--WITH COPROCESSOR ITEM PART NUMBER DESCRIPTION 9 CA400677-001 ASSY PCB MEGA STE/1 W/M USA 9 CA400677-002 ASSY PCB MEGA STE/1 W/M CAN 9 CA400677-003 ASSY PCB MEGA STE/1 W/M UK 9 CA400677-005 ASSY PCB MEGA STE/1 W/M GER 9 CA400677-006 ASSY PCB MEGA STE/1 W/M ITA 9 CA400677-007 ASSY PCB MEGA STE/1 W/H NET-UK 9 CA400677-008 ASSY PCB MEGA STE/1W/M NET-FRA 9 CA400677-009 ASSY PCB MEGA STE/1 W/H SPA 9 CA400677-010 ASSY PCB MEGA STE/1 W/M SWG 9 CA400677-011 ASSY PCB MEGA STE/1 W/M MEXICO 9 CA400677-012 ASSY PCB MEGA STE/1 W/M SWD 9 CA400677-014 ASSY PCB MEGA STE/1 W/M AUS 9 CA400677-020 ASSY PCB MEGA STE/1 W/M SWF 2 MEGABYTES MEMORY--WITHOUT COPROCESSOR ITEM PART NUMBER DESCRIPTION 9 CA400677-301 ASSY PCB MEGA STE/2 W/M USA 9 CA400677-302 ASSY PCB MEGA STE/2 W/M CAN 9 CA400677-303 ASSY PCB MEGA STE/2 W/M UK 9 CA400677-305 ASSY PCB MEGA STE/2 W/M GER 9 CA400677-306 ASSY PCB MEGA STE/2 W/M ITA 9 CA400677-307 ASSY PCB MEGA STE/2 W/M NET-UK 9 CA400677-308 ASSY PCB MEGA STE/2W/M NET-FRA 9 CA400677-309 ASSY PCB MEGA STE/2 W/M SPA 9 CA400677-310 ASSY PCB MEGA STE/2 W/M SWG 9 CA400677-311 ASSY PCB MEGA STE/2 W/M MEXICO 9 CA400677-312 ASSY PCB MEGA STE/2 W/M SWD 9 CA400677-314 ASSY PCB MEGA STE/2 W/M AUS 9 CA400677-320 ASSY PCB MEGA STE/2 W/M SWF 9 CA400677-304 ASSY PCB MEGA STE/2PERITEL FRA2 MEGABYTES MEMORY--WITH COPROCESSOR ITEM PART NUMBER DESCRIPTION 9 CA400677-201 ASSY PCB MEGA STE/2 W/M USA 9 CA400677-202 ASSY PCB MEGA STE/2 W/M CAN 9 CA400677-203 ASSY PCB MEGA STE/2 W/M UK 9 CA400677-205 ASSY PCB MEGA STE/2 W/M GER 9 CA400677-206 ASSY PCB MEGA STE/2 W/M ITA 9 CA400677-207 ASSY PCB MEGA STE/2 W/M NET-UK 9 CA400677-208 ASSY PCB MEGA STE/2W/M NET-FRA 9 CA400677-209 ASSY PCB MEGA STE/2 W/M SPA 9 CA400677-210 ASSY PCB MEGA STE/2 W/M SWG 9 CA400677-211 ASSY PCB MEGA STE/2 W/M MEXICO 9 CA400677-212 ASSY PCB MEGA STE/2 W/M SWD 9 CA400677-214 ASSY PCB MEGA STE/2 W/M AUS 9 CA400677-220 ASSY PCB MEGA STE/2 W/M SWF 4 MEGABYTE MEMORY--WITHOUT COPROCESSOR ITEM PART NUMBER DESCRIPTION 9 CA400677-501 ASSY PCB MEGA STE/4 W/M USA 9 CA400677-502 ASSY PCB MEGA STE/4 W/M CAN 9 CA400677-503 ASSY PCB MEGA STE/4 W/M UK 9 CA400677-505 ASSY PCB MEGA STE/4 W/M GER 9 CA400677-506 ASSY PCB MEGA STE/4 W/M ITA 9 CA400677-507 ASSY PCB MEGA STE/4 W/M NET-UK 9 CA400677-508 ASSY PCB MEGA STE/4W/M NET-FRA 9 CA400677-509 ASSY PCB MEGA STE/4 W/M SPA 9 CA400677-510 ASSY PCB MEGA STE/4 W/M SWG 9 CA400677-511 ASSY PCB MEGA STE/4 W/M MEXICO 9 CA400677-512 ASSY PCB MEGA STE/4 W/M SWD 9 CA400677-514 ASSY PCB MEGA STE/4 W/M AUS 9 CA400677-520 ASSY PCB MEGA STE/4 W/M SWF 9 CA400677-504 ASSY PCB MEGA STE/4PERITEL FRA4 MEGABYTE MEMORY--WITH COPROCESSOR ITEM PART NUMBER DESCRIPTION 9 CA400677-401 ASSY PCB MEGA STE/4 W/M USA 9 CA400677-402 ASSY PCB MEGA STE/4 W/M CAN 9 CA400677-403 ASSY PCB MEGA STE/4 W/M UK 9 CA400677-405 ASSY PCB MEGA STE/4 W/M GER 9 CA400677-406 ASSY PCB MEGA STE/4 W/M ITA 9 CA400677-407 ASSY PCB MEGA STE/4 W/M NET-UK 9 CA400677-408 ASSY PCB MEGA STE/4W/M NET-FRA 9 CA400677-409 ASSY PCB MEGA STE/4 W/M SPA 9 CA400677-410 ASSY PCB MEGA STE/4 W/M SWG 9 CA400677-411 ASSY PCB MEGA STE/4 W/M MEXICO 9 CA400677-412 ASSY PCB MEGA STE/4 W/M SWD 9 CA400677-414 ASSY PCB MEGA STE/4 W/M AUS 9 CA400677-420 ASSY PCB MEGA STE/4 W/M SWF CONTROLLER BOARDS ITEM PART NUMBER DESCRIPTION 1 CA200535-001 HDD ASSY I/F LST-1/2/4 KEYBOARD/MOUSE ASSEMBLIES ITEM PART NUMBER DESCRIPTION CA400732-001 K/B MEGA STE USA CA400732-003 K/B MEGA STE UK CA400732-004 K/B MEGA STE FRA CA400732-005 K/B MEGA STE GER CA400732-006 K/B MEGA STE ITA CA400732-009 K/B MEGA STE SPA CA400732-010 K/B MEGA STE SWISS CA400732-012 K/B MEGA STE SWD CA070025 MOUSE ST/STE/MEGA DISK DRIVES ITEM PART NUMBER DESCRIPTION C103704-001 FDD 1MB 3.5" SONY W/LED POWER SUPPLY ITEM PART NUMBER DESCRIPTION C302074-001 PSU PHIHONG PSM 5341 FCC MEMORY ITEM PART NUMBER DESCRIPTION 8 CA400960-003 ASSY SIMM MODULE 512K X 8 8 CA400960-002 ASSY SIMM MODULE 1M X 8 8 CA400960-001 ASSY SIMM MODULE 1M X 8 ROM SETS ITEM PART NUMBER DESCRIPTION 11 CA400857-001 ASSY IC TOS 2.05 USA 11 CA400857-003 ASSY IC TOS 2.05 UK 11 CA400857-004 ASSY IC TOS 2.05 FRA 11 CA400857-005 ASSY IC TOS 2.05 GER 11 CA400857-006 ASSY IC TOS 2.05 ITA 11 CA400857-009 ASSY IC TOS 2.05 SPA 11 CA400857-010 ASSY IC TOS 2.05 SWG 11 CA400857-012 ASSY IC TOS 2.05 SWD 11 CA400857-020 ASSY IC TOS 2.05 SWF INTEGRATED CIRCUITS AND COMPONENTS ITEM PART NUMBER DESCRIPTION U004,U005 C302017-001IC SRAM 8K X 8 85NS U008,U009 C301846-001IC CTRAM 8K X 8 35NS U007 C398778-001IC 68000 PLCC 16 MHZ U405 C026028-002IC 1772 FDD CONTROLLER UB02 C101718-101IC MC68881 16 MHz U501 C301705-001IC IMP GLUE CUSTOM TT U502 C301712-001IC SHIFTER UA3 C301899-001IC PAL 16R4 UA2 C301901-001IC PAL 20L8 UB01 C301903-001IC PAL 16L8 U6 C301904-001IC GAL 22V10 U12 C301905-001IC PAL 16L8 U3 C301906-001IC GAL 22V10 U2 C301907-001IC PAL 16R4B U904 C301908-001IC PAL 16L8A U407 C301909-001IC GAL 22V10 U306 C398106-001IC MC68901 UA04 C398109-001IC Z85C30 10 MHz U11 C301898-001IC GAL 22V10 U404 C398739-001IC DMA U205 C101643 IC CUSTOM ST BLITTER 21 C301020-001 BATTERY 3.6V SEPARATE ROMS ITEM PART NUMBER DESCRIPTION 11 C302018-002IC ROM MEGASTE TOS 2.05 E USA 11 C302019-002IC ROM MEGASTE TOS 2.05 O USA 11 C302020-002IC ROM MEGASTE TOS 2.05 E UK 11 C302021-002IC ROM MEGASTE TOS 2.05 O UK 11 C302022-002IC ROM MEGASTE TOS 2.05 E FRA 11 C302023-002IC ROM MEGASTE TOS 2.05 O FRA 11 C302024-002IC ROM MEGASTE TOS 2.05 E GER 11 C302025-002IC ROM MEGASTE TOS 2.05 O GER 11 C302026-002IC ROM MEGASTE TOS 2.05 E ITA 11 C302027-002IC ROM MEGASTE TOS 2.05 O ITA 11 C302028-002IC ROM MEGASTE TOS 2.05 E SPA 11 C302029-002IC ROM MEGASTE TOS 2.05 O SPA 11 C302030-002IC ROM MEGASTE TOS 2.05 E SWF 11 C302031-002IC ROM MEGASTE TOS 2.05 O SWF 11 C302032-002IC ROM MEGASTE TOS 2.05 E SWG 11 C302033-002IC ROM MEGASTE TOS 2.05 O SWG 11 C302034-002IC ROM MEGASTE TOS 2.05 E SWD 11 C302035-002IC ROM MEGASTE TOS 2.05 O SWD CABLE ASSEMBLIES ITEM PART NUMBER DESCRIPTION 3 CA400335-002 ASSY CABLE HDD MEGA STE 4 CA400336-002 ASSY CABLE FDD MEGA STE LED ASSEMBLIES ITEM PART NUMBER DESCRIPTION CA400365-002 ASSY CABLE HDD/LED 180MM YELLOW CA400972-001 CABLE PWR ASSY 150MM DISK DRIVE CA400365-003 ASSY CABLE PWR/LED 550MM GREEN MECHANICAL ASSEMBLIES ITEM PART NUMBER DESCRIPTION 7 C300839-002 VME FILLER PANEL W/SERIAL HOLE 17 C301663-002 VME FILLER PNL MEGA STE CA400418-001 ASSY CABLE DB9(W/CONN SCREW) 24 C301562-001 BTM CASE MEGA STE 12 C300845-002 COVER HDD ACCESSORY MEGA STE CA400417-002 ASSY VME FILLER PANEL MEGA STE 10 CA400855-001 ASSY TOP CASE MEGA STE C300840-001 BRKT FLOPPY DRIVE C301894-001 BRKT RETAINER LED C300741-002 COVER HDD ACCESSORY MEGA STE C300835-001 SHIELD HARD DISK C300841-001 BRKT HARD DISK C070012 RUBBER FOOTSECTION EIGHT SCHEMATICS AND PCB SILKSCREEN SECTION NINE GLOSSARY OF PART NAMES AND TERMS BUS ERROR GSTMCU has asserted BERR to inform the processor that there is a problem with the current cycle. This could be due to a device not responding (for example, CPU tries to read memory but the Memory Controller fails to assert DTACK), or an illegal access (attempting to write to ROM). A bus error causes exception processing. CPU the 68000 microprocessor. DMA direct memory access. Process in which data is transferred from external storage device to RAM, or from RAM to external storage. Transfer is very fast, takes place independent of the CPU, so the CPU can be processing while DMA is taking place. GSTMCU arbitrates the bus between the CPU and DMA. DMA CONTROLLER Atari proprietary chip which controls the DMA process. All disk I/O goes through this device. EXCEPTION a state in which the processor stops the current activity, saves what it will need to resume the activity later in RAM, fetches a vector (address) from RAM, and starts executing at the address vector. When the exception processing is done, the processor will continue what it was doing before the exception occurred. Exceptions can be caused by interrupts, instructions, or error conditions. See also Section Two, System Errors, or a 68000 reference for more detail. HALT state in which the CPU is idle, all bus lines are in the high-impedence state, and can only be ended with a RESET input. This is a bi-directional pin on the CPU. It is driven externally by the RESET circuit on power-up or a reset button closure, and internally when a double bus fault occurs. A double bus fault is an error during a sequence which is run to handle a previous error. For example, if a bus error occurs, and during the exception processing for the bus error, another bus error occurs, then the CPU will assert HALT. HSYNC timing signal for the video display. Determines when the horizontal scan is on the screen, and when it is blank (retracing). The synchronization (approx. every 63 microseconds) also is encoded onto IPL1,2 as an interrupt to the CPU. INTERRUPT a request by a device for the processor to stop what it is doing and perform processing for the device. It is a type of exception. Interrupts are maskable in software, meaning they will be ignored if they do not meet the current priority level of the CPU. There are three priorities: the highest are MFP interrupts, then VSYNC interrupts, and lowest are HSYNC interrupts. Interrupts are signaled to the CPU on the Interrupt Priority Level inputs (IPL0-2). See Theory of Operation, Main System, MFP, and GSTMCU. GSTMCU Atari proprietary chip which handles all RAM accesses. See Theory of Operation, Main System and Video Subsystem for details. MIDI Musical Instrument Digital Interface. An electrical standard by which electronic instruments communicate. Also, the logical system for such communication. In the MegaSTer, consists of a 6850 communications chip, driver and receiver chips (74LS04, 74LS05, and PC-900 photocoupler), and an MFP interrupt channel. MFP Multi-function Peripheral, also 68901. Interrupt control, timers, and USART for RS232 communication. See Theory of Operation, Main System. MODULATOR device which combines video signals R,G,B, VSYNC, and HSYNC into a composite signal for monitors requiring this type input, and also modulates this signal, combined with audio, onto an RF carrier for output to a television. PLL Phase Locked Loop ia a circuit which locks the horizontal sync signal onto the color burst reference frequency for accurate color on the T.V. Without this circuit, colors on the T.V. become unstable, flickering or shifting about on the screen. PSG Programmable Sound Generator, also YM2149. Yamaha version of General Instruments AY-3-8910. Has two 8 bit I/O ports and three sound channels. Used in parallel port and audio. RS232C Electical standard for serial digital communication. Also the physical and logical device which performs communication using this standard. In the STr computers, consists of the MFP, PSG, 1488, and 1489 chips. 1772 Western Digital Floppy Disk Controller. 6850 also ACIA (Asynchronous Communication Interface Adapter). Interfaces between 8 bit parallel bus and serial communication bus. In the STr, there are two 6850s, one for keyboard communication, and one for MIDI communication. 68901 see MFP. Supervisor Mode state of the CPU in which it is allowed to access all hardware and RAM locations, and perform some privileged instructions. Determined by the state of a bit in the Status Register. The operating system operates in supervisor mode, and switches to user mode before passing control to an application (although the application can enter supervisor mode if it wishes). User Mode state of the CPU in which certain instructions and areas in the memory map are disallowed (resulting in a privilege violation exception if attempted). See also SUPERVISOR MODE. VSYNC signal used for vertical synchronization of CRT display device. Occurs at 70 Hz (monochrome), or 50 or 60 Hz color. YM2149 see PSG. VME Slot On/Off Switch AC Input Fan Audio R Floppy Monitor TV ACSI Printer Modem 2 Audio L Modem 1