HOST = 0
TOS = 0
	.include hardware
	.include defs
	.include nvram

 	.include e_data
	.extern ebltmsg,got_blt
	.extern testexp

*	Software designer: Tom Le
*	Company: Atari Microsystem
*	Date: 3/30/92
*	Testing expansion port
* 4/17/92 TLE Added the expansion blitter test (long and short)
*         TLE Fixed bug in the priority test to run at 16 MHZ
*         TLE Modified e_excep to recover from TRAPV
*	  TLE Removed e_blt, and modified blt, and xblt
* 7/9/92  TLE Removed the BLT test message, and fix bug when running 
*             expansion test from the cartridge ROM.

	.include e_var
*	.include e_dspreg	;moved to e_var, TLE
*	.include e_excep	;moved to e_var, TLE

	.text
e_expbe:
	move.l  a2,8
	move.l  a4,sp
.if TOS=0
	move.w  #red,palette
.endif
	lea	msgexpno,a5
	bsr	dspmsg
	rts

testexp:
	move.l  #blt2,Blt		;add new variable for exp Blitter TLE
	move.l	#ebltmsg,Bltmsg		;add new variable for exp Blitter TLE

	lea	msgexp,a5
	bsr	dsptst
	move.l  8,a2	
	move.l  sp,a4
	move.l  #e_expbe,8
	move.w  blt2,d0		;is expansion fixture connected
	move.l  a2,8
	bsr	saveexcep
	bsr	getexcep
	clr.w   flag		;clear all possible failure
	bsr	testlat
	bsr	testber
	bsr	testint1
	bsr	testint3

;	bsr	testint5
	bsr	testint6
	bsr	test500
	bsr	testhalt

	clr.b   erflg0		;7/9/92 TLE tried to
        clr.b   erflg1		;   remove
	bsr	got_blt		;   the blt test message

;	bsr	testxblt
	bsr	testpri
	bsr	crlf
	tst.w   flag		;any failure?
	beq.s   testexpp
        movea.l   #falmsg,a5
	move.b	#t_XBUS,d0
        bsr       dsppf
	bra	testexprt
testexpp:
        movea.l   #pasmsg,a5
	move.b	#t_XBUS,d0
        bsr       dsppf

testexprt:
	bsr	resexcep
;	move.b  #1,expandio	; TLE, bugs kill the expansion test
	rts

; .include e_lat
latbe:				;bus error routine  
	move.l  spsave0,sp
	bra	latch1
	rte	

latbeer:				;bus error routine  
	move.l  spsave0,sp
	bra	latch1er
	rte	

testlat:
	movea.l #$0000,a0	;start test address
	move.l  #$10000,d2	;test address increment
	lea     expandio,a1 	;address latch
	move.w  sr,srsave0
	move.l  sp,spsave0
	move.l  8,besave0
	move.l  #latbe,8	;load the latch bus error routine
	move.w  #$2700,sr	;
	
;	move.b  #1,(a1)	 ;enable address latch
	move.b (a1),d0	 ;TOM 5/29/92   
	and.b  #$f,d0	 ;TOM 5/29/92
	move.b   d0,(a1) ;TOM 5/29/92 enable address latch
	move.b   (a0),d1		;  and clear it

latch:
;	move.b  #1,(a1)		;enable address latch
	move.b (a1),d0	 ;TOM 5/29/92
	and.b  #$f,d0	 ;TOM 5/29/92
	move.b   d0,(a1) ;TOM 5/29/92 
	move.b  (a0),d1		;latch a16-a23

latch1:
	move.w  (a1),d1		;read from latch
	and.l   #$ff,d1		;
	swap    d1
	cmp.l   d1,a0
	bne     latcher
latch2:
	add.l   d2,a0
	cmp.l   #$1000000,a0
	blt     latch
	
latchrt:
	move.w  srsave0,sr
	move.l  spsave0,sp
	move.l  besave0,8
	btst    #elatf,flag
        rts

latcher:
	swap    d1
	move.l  a0,d0
	swap    d0
.if TOS=0
        move    #red,palette
.endif
        lea     latchmsg,a5
	bsr	dspmsg
	bsr     dspa0	;fail address
	bsr	dspspc
	bsr     dspd0b
	bsr	dspspc
	bsr     dspd1b
	lea	expandio,a1
	move.b  1(a1),d1
	bsr	dspspc
	bsr	dspd1b
	bsr	dspspc
	bsr	dspd2w
	bset    #elatf,flag
	bra	latchrt

	bra failloop
failloop:
	move.l  #latbeer,8	;load the latch bus error routine

latchl:

	move.b  #1,(a1)		;enable address latch
	move.b  (a0),d1		;latch a16-a23, and reset

latch1er:
	move.w  (a1),d1		;read from latch
	bra     latchl

;  .include e_ber
excepbebe:
	move.l  spsave0,sp
	bra	testber0
	rts

testber:
	move.l  sp,spsave0
	move.l  8,intsave0
	move.l  #excepbebe,8
        lea     expandio,a0
	move.b  2(a0),d0 		;clear bus error
	move.w   #0,$f10000		;set bus error bit

testber0:
	move.b  (a0),d0
	btst	#wasber,d0
	beq	tberhi	;stuck hi

tbert:
	move.l  intsave0,8
	btst    #eberf,flag
        rts

tberhi:
.if (TOS = 0)
        move    #red,palette
.endif
	lea	testbeh,a5
	bsr	dspmsg
	bset    #eberf,flag
	bra	tbert

*  .include e_int6
eint6:				;
        move.w  #$6789,intword
	bsr	clear_io
	rte

eint6sp:		;for spurious int
	lea	spurina0,a5
	bsr	dspmsg
	bsr	clear_io
	rte

testint6:
	move.b  #int6,intlev
	bsr	loadvect
	move.l  $60,spurisave		;
	move.l  #eint6sp,$60
	move.l  intvect,intsave0	;save the OP int routine
	move.l  #eint6,intvect  	;
	move.l  #10,d2		;setup a sw timer
	clr.w   intword	        ;
	bsr	set_io		;gen int

testint6a:
	move.w  intword,d0
	cmp.w   #$6789,d0
	beq     testint6p	
	sub.l   #1,d2
	bne    testint6a
	bsr	clear_io
.if TOS=0       
        move    #red,palette
.endif
	lea     int6msg1,a5
	bsr	dspmsg
	bset    #eint6f,flag

testint6r:
	move.l  intsave0,intvect	;restore int
	move.l  spurisave,$60		;
	btst    #eint6f,flag
        rts

testint6p:
	bra	testint6r

*  .include e_int3
spurint:			;ste int3 only
	bsr	clear_io
        move.w  #$4567,intword
	rte

int3auto:			;sparrow int3 only
	bsr	clear_io
        move.w  #$3456,intword
	rte

testint3:
	move.b  #int3,intlev
	move.l  #spurint,$60    ;
	move.l  #int3auto,$6c    ;
	move.w  sr,srsave0	;
	move.w  sr,d0
	and.w   #$f8ff,d0	;
	or.w    #$0200,d0	;enable int3 
	move.w  d0,sr

	clr.w   intword	        ;
	bsr	set_io
	move.l  #$800,d1        ;setup a sw timer

testint3a:
	move.w  intword,d0
	cmp.w   #$3456,d0
	beq     testint3p	
	sub.l   #1,d1
	bne     testint3a
	bsr	clear_io
.if TOS=0
        move    #red,palette
.endif
	lea     int3msg1,a5
	bsr	dspmsg
	bset   #eint3f,flag

testint3r:
	move.w  srsave0,sr	;
	btst    #eint3f,flag
        rts

testint3p:
	bra	testint3r

*  .include e_500
test500:
	move.b   #khzhi,intlev
	bsr	set_io
	move.b  expandio,d2	;get latchen bit
	bsr	clear_io
	btst	#latchen,d2
	beq	t500lo		;stuck low

	move.b   #khzlo,intlev
	bsr	set_io
	move.b  expandio,d2	;get latchen bit
	bsr	clear_io
	btst	#latchen,d2
	bne	t500hi		;stuck hi

t500rt:
	btst    #e500f,flag
        rts

t500lo:
.if TOS=0
        move    #red,palette
.endif
	lea	test500l,a5
	bsr	dspmsg
	bset    #e500f,flag
	bra	t500rt

t500hi:
.if TOS=0
        move    #red,palette
.endif
	lea	test500h,a5
	bsr	dspmsg
	bset    #e500f,flag
	bra	t500rt

*  .include e_halt
timeria0:
	move.w  #$3456,intword
	lea	mfp,a0
	clr.b   tacr(a0)	;stop timer
	moveq	#13,d0
	jsr	disint		;disable int
        rte

testhalt:
	lea	mfp,a0
	move.l  #$50,d0
testhaltw:
	sub.l   #1,d0
	cmp.l   #0,d0
	bne	testhaltw

	bsr	save_tmr
	move.b  #0,imra(a0)
	move.b  #0,imrb(a0)

	move.l  timerint,inttmrsave ;save interrupt
	move.l	#timeria0,timerint ; Set interrupt vector
	clr.w   intword
	bsr	gotimer		;start timer A
	move.b  #halten,intlev
	bsr	set_io		;halt the CPU
	moveq	#2,d2		

thalt0:
	sub.w   #1,d2
	cmp.w   #$3456,intword	
	beq.s	thaltp		;
	cmp.w   #00,d2
	bgt	thalt0
	bset    #ehaltf,flag	;set error
.if TOS=0
        move    #red,palette
.endif
	lea	testhaltm,a5
	bsr	dspmsg

thaltrt:
	move.l  inttmrsave,timerint ;
	bsr	res_tmr
	btst    #ehaltf,flag
        rts

thaltp:
	bra	thaltrt

gotimer:
	movea.l	#mfp,a0		;
	clr.b	tacr(a0)
	move.b	#6,tadr(a0)     ; 1 counts at 2.4576 MHz / 200 = 325.5 us
	move.b	keyboard,d0	;read stat to assure no irq at 6850
	move.b	iodata+keyboard,d0  ;clear data buffer
	moveq	#13,d0		;timer A
	jsr	enabint		;set enable, mask bits
	move.b	#7,tacr(a0)	;start timer /200
	rts

res_tmr:
	movea.l	#mfp,a0		;
	move.b  imra_save,imra(a0)
	move.b  iera_save,iera(a0)
	move.b  isra_save,isra(a0)
	move.b  ipra_save,ipra(a0)
	move.b  imrb_save,imrb(a0)
	move.b  tadr_save,tadr(a0)
	move.b  tacr_save,tacr(a0)
	rts

save_tmr:
	movea.l	#mfp,a0		;
	move.b  imra(a0),imra_save
	move.b  iera(a0),iera_save
	move.b  isra(a0),isra_save
	move.b  ipra(a0),ipra_save
	move.b  imrb(a0),imrb_save
	move.b  tadr(a0),tadr_save
	move.b  tacr(a0),tacr_save
	rts

* .include e_int1
spurint1:			;
	bsr	clear_io
	lea	spurina1,a5
	bsr	dspmsg
        move.w  #$1234,intword
	rte

eint1a:
	bsr	clear_io
        move.w  #$3456,intword
	bclr    #eint1f,flag
	rte

testint1:
	bset	#eint1f,flag
	move.w  #$abcd,intword
	move.b  #int1,intlev
	move.l  $60,intsave0
	move.l  #spurint1,$60    ;
	move.l  #eint1a,int1auto
	move.w  sr,srsave0	;
	move.w  sr,d0
	and.w   #$f8ff,d0	;
	move.w  d0,sr
	bsr	set_io
	move.l  #$800,d2        ;setup a sw timer
	
testint1a:
	move.w  intword,d0
	cmp.w   #$3456,d0
	beq     testint1p	;passed
	sub.l   #1,d2
	bne     testint1a
	btst    #eint1f,flag
	beq	testint1p	;passed
	bsr	clear_io
	
.if (TOS=0)
        move    #red,palette
.endif
	lea     int1msg1,a5
	bsr	dspmsg
	bset  #eint1f,flag

testint1r:
	move.l  intsave0,$60
	move.w  srsave0,sr	;
        btst    #eint1f,flag
        rts

testint1p:
	bclr    #eint1f,flag
	bra	testint1r

* .include e_int5
spurint5:			;
	bsr	clear_io
	lea	spurina5,a5
	bsr	dspmsg
        move.w  #$1234,intword
	rte

eint5:			;
	bsr	clear_io
        move.w  #$4567,intword
	rte

testint5:
;	move.l  #spurint5,$60    ;
	move.b  #int5,intlev
	bsr	loadvect
	move.l  intvect,intsave0	;save the OP int routine
	move.l  #eint5,intvect  ;
	move.l  #10,d1		;setup a sw timer
	clr.w   intword	        ;clear int flag
	bsr	set_io

testint5a:
	move.w  intword,d0
	cmp.w   #$4567,d0
	beq     testint5p	
	sub.l   #1,d1
	bne     testint5a
	bsr	clear_io
.if (TOS=0)
        move    #red,palette
.endif
	lea     int5msg1,a5
	bsr	dspmsg
	bset    #eint5f,flag

testint5r:
	move.l  intsave0,intvect  ;save the OP int routine
	btst    #eint5f,flag
        rts

testint5p:
	bra	testint5r

*  .include e_blt 	;move to blt.s file TLE 17 APR 92

*  .include e_pri

eint6p:				;
	movem.l d0-d1,-(sp)
	bsr	clear_io	;clear interrupt
	lea	expandio,a0
	move.b  #0,2(a0)	;negates XIEO to disable MFP int
	move.w  #$789a,intword6
;  move.w intword6,d0
;  bsr	crlf
;  bsr	dspd0w
	movem.l (sp)+,d0-d1
	rte

spurip:
	movem.l d0-d1,-(sp)
	move.w  #$1234,intword
 ; move.w intword,d0
 ; bsr	crlf
 ; bsr	dspd0w
	lea	mfp,a0
	clr.b   tacr(a0)	;stop timer
	moveq	#13,d0
	jsr	disint		;disable int
	movem.l (sp)+,d0-d1
	rte

buserrp:
	move.w  #$bebe,intword
 ; move.w intword,d0
 ; bsr	crlf
 ; bsr	dspd0w
	move.l  stacksave,sp
	move.l  pcsave,a6
	jmp     (a6)
	rte

testpri:
	move.b  SPControl,d0
	move.b  d0,savectl
	bset    #7,d0
	move.b  d0,SPControl

	clr.w   intflg	        ;
	clr.w   intword
	clr.w   intword6
	lea	mfp,a0
	bsr	save_tmr
	move.b  #0,imra(a0)
	move.b  #0,imrb(a0)
	move.b  #int6,intlev	;
	move.l  $60,intsave0
	move.l  8,besave0
	move.l  timerint,inttmrsave ;save tmr interrupt
	move.l  intvect,int6save	;save the OP int routine
	move.l  #eint6p,intvect  ;
	move.l	#timeria0,timerint ; Set interrupt vector
	move.l  #spurip,$60
	bsr	loadvect
;	move.l  #$f000,d1	;setup a sw timer
	bsr	set_io		;
	move.l  #$f000,d1	;setup a sw timer

testpril:
	move.w  intword6,d0
	cmp.w   #$789a,d0
	beq     testpric	;continue testing	
	sub.l   #1,d1
	bne    testpril       

testprif:
.if (TOS=0)
        move    #red,palette
.endif
	lea     primsg1,a5
	bsr	dspmsg
	bset    #eprif,flag

testprir:
	move.b  savectl,d0
	move.b  d0,SPControl
	move.l  intsave0,$60
	move.l  inttmrsave,timerint 	;restore interrupt
	move.l  int6save,intvect	;restore int
	move.l  besave0,8	
	bsr	res_tmr
	btst    #eprif,flag
        rts

testprip:
	bra	testprir

testpric:
	move.l  sp,stacksave
	move.l  #testprif,pcsave
	move.l  #buserrp,8
	bsr	gotimer		;start timer A

testpri3:
	move.l  #$f000,d1	;setup a sw timer

testpril1:
	move.w  intword,d0
	cmp.w   #$1234,d0	;spuri interrupt?
	beq     testprip	;
	sub.l   #1,d1
	bne    testpril1
	bra	testprif	;

*  .include e_mess
   .data
msgexc14: dc.b cr,lf,'  $14: Zero  Divide ',eot
msgexc18: dc.b cr,lf,'  $18: CHK,CHK2 instruction ',eot
msgexc1c: dc.b cr,lf,'  $1c: TRAP instruction ',eot
msgexc20: dc.b cr,lf,'  $20: priviledge violation ',eot
msgexc24: dc.b cr,lf,'  $24: Trace exception ',eot
msgint5v: dc.b cr,lf,'  Int 5 user vector  ',eot
msgint6: dc.b cr,lf,'   Int 6 user vector  ',eot
msgint1a: dc.b cr,lf,'  Int 1 auto vector  ',eot
spurina5: dc.b cr,lf,'  Spurious int 5  ',eot
spurina1: dc.b cr,lf,'  Spurious int 1  ',eot
spurina6: dc.b cr,lf,'  Spurious int 6  ',eot
msgbe6: dc.b cr,lf,'  Bus error from int level 6  ',eot
msgbe0: dc.b cr,lf,'  Bus error ',eot
spurina0: dc.b   cr,lf,'  Spurious Interrupt ',eot
msgii0: dc.b    cr,lf,'  Illegal Instruction  ',eot     
msgae0: dc.b    cr,lf,'  Address Error  ',eot
msgaccadd: dc.b    ' Access Address: ',eot
msgpc:  dc.b    ' Program Counter: ',eot

mess1: dc.b cr,lf,'  Block test: ',eot
mess2: dc.b cr,lf,'  Adddress test: ',eot
mess3: dc.b cr,lf,'  Hilo test: ',eot
mess4: dc.b cr,lf,'  Copy test: ',eot
testhaltm: dc.b cr,lf,'  Halt Test failed  ',eot
msgtmr: dc.b cr,lf,'      timer int...: ',eot
test500l: dc.b cr,lf,'  500 KHZ clock stuck low',eot
test500h: dc.b cr,lf,'  500 KHZ clock stuck high',eot
prnfmsg:  dc.b cr,lf,'  printer is not responding... ',eot
prnmsg0:  dc.b cr,lf,'  printer is working',eot
testbel: dc.b cr,lf,'  BERR stuck low',eot
testbeh: dc.b cr,lf,'  BERR stuck high',eot
bltmsg1:  dc.b cr,lf,'  Blitter test failed  ',eot
bemsg:   dc.b '*',eot
msgtr:  dc.b cr,'  Testing Target Ram               Test No. ',eot
msgtrq: dc.b cr,'  Testing Videl Data Latch         Test No. ',eot
msgexpram: 
	dc.b cr,'  Testing Expansion Ram            Test No. ',eot
msgexp: dc.b  'Testing Expansion ',eot
msgexpno: dc.b cr,lf,'  Check the Expansion Blitter or Cables ',eot

.if !(^^defined falmsg)
failmsg: dc.b    tab,'Failed: ',eot
falmsg = failmsg
.endif

.if !(^^defined pasmsg)
passmsg: dc.b    tab,'Passed: ',eot
pasmsg = passmsg
.endif

latchmsg: dc.b cr,lf,'  Address Latch failed at addr\exp\read: ',eot
int1msg1: dc.b cr,lf,'  Int. 1 failed ',eot
int3msg1: dc.b cr,lf,'  Int. 3 failed ',eot
int5msg1: dc.b cr,lf,'  Int. 5 failed ',eot
int6msg1: dc.b cr,lf,'  Int. 6 failed ',eot
primsg1: dc.b cr,lf,'  Int. priority failed ',eot
rammsg1: dc.b     cr,lf,'  RAM test start.end: ',eot
ramfmsg: dc.b    cr,lf,'    RAM failed addr.write.read: ',eot
startmsg: dc.b   'Testing in progress sp/sr: ',eot
donemsg2: dc.b    cr,lf,lf,'Test is done sp/sr: ',eot
spacemsg: dc.b   '  ',eot
crlfmsg: dc.b    cr,lf,eot
crmsg: dc.b    cr,eot