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15.12 MegaSTE Bus


MegaSTE internal Bus connector

Mega-ST-Bus:                   Power Supply Connector:
(top view)                     (top view)

D4      <>  1 * *  2  D5       +5V  1 *
D3      <>  3 * *  4  D6       +5V  2 *
D2      <>  5 * *  6  D7       GND  3 *
D1      <>  7 * *  8  D8       GND  4 *
D0      <>  9 * * 10  D9       GND  5 *
*AS      > 11 * * 12  D10      +12V 6 *
*UDS     > 13 * * 14  D11
*LDS     > 15 * * 16  D12      Adress Strobe
R/*W     > 17 * * 18  D13      Upper/Lower Data Strobe
*DTACK  <  19 * * 20  D14      Read/*Write
*BGO     > 21 * * 22  D15      Data Transfer ACKnowledge
*BGACK  <  23 * * 24 (GND)     Bus Grant Out
*BR     <  25 * * 26  A23      Bus Grant ACKnowledge
(GND)      27 * * 28  A22      Bus Request
CLK     >  29 * * 30  A21      CLocK
(GND)      31 * * 32 (GND)
*HALT    > 33 * * 34  A20
*RESET   > 35 * * 36  A19
*VMA     > 37 * * 38  A18      Valid Memory Adress
E        > 39 * * 40  A17      Enable Clock
*VPA    <  41 * * 42  A16      Valid Pheripheral Adress
*BERR    > 43 * * 44  A15      Bus ERRor
*NMI    <  45 * * 46  A14      Not Maskable Interupt (level 7)
*INT 5  <  47 * * 48  A13      INTerrupt level 5
*INT 3  <  49 * * 50  A12      INTerrupt level 3
FC2      > 51 * * 52  A11      Function Code 2
FC1      > 53 * * 54  A10      Function Code 1
FC0      > 55 * * 56  A9       Function Code 0
A1      <> 57 * * 58  A8
A2      <> 59 * * 60  A7
A3      <> 61 * * 62  A6
A4      <> 63 * * 64  A5

<> signal direction
even pins: all signals are bidirectional

*signal: active low

Source: Atari ST Profibuch

Und das ganze noch einmal als Grafik, nur mit Pin-Beschriftung.




Abbildung 1 - MegaST(e) interner Bus








Copyright © Robert Schaffner (doit@doitarchive.de)
Letzte Aktualisierung am 23. Mai 2004
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