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8.1.1 Atari ST MFP
Der MFP 68901 im Atari
MFP ist eine Abkürzung, hinter der sich das folgende
"Langwort" Multi-Funktion-Peripheral-Baustein versteckt. was
auch nicht gelogen ist. Dieses IC ist ein kleines Wunderwerk, in dem
sich einige Funktionen verstecken.
- 8 Bit Parallelport - Datenrichtung eines Portbits separat Programmierbar - Verwendung eines Portbits als Interrupteingang (siehe ST) - verschiedene Interruptquellen - Vier programmierbare universal Timer und eine serielle Schnittstelle Diese Funktionen sind nun alle in einem Gehäuse
untergebracht, das dieses etwas Platz beansprucht fällt dann an
dem 52 poligen Baustein schnell auf. Ich will an dieser Stelle
für die mehr Hardware orientierten Freaks auch die komplette
Pinbelegung dieses und des MFP-Bausteines des alten ST ablichten. So
werden die Unterschiede am deutlichsten.
Pinbelegung des MFP im ST und im Falcon F030:
Der MFP im ST befinden sich im 48 Pin DIL-Gehäuse.
Der MFP im Falcon besitzt hingegen ein 52 poliges PLCC-Gehäuse!
PIN FUNKTION ST FALCON PIN FUNKTION ST FALCON
---------------------------------------------------------------
52 - CS
1 R/W NC 51 - DS
2 A1 RXW 50 - DTACK
3 A2 RS1 49 - IACK
4 A3 RS2 48 CS D7
5 A4 RS3 47 DS D6
6 A5 RS4 46 DTACK D5
7 TC RS5 45 IACK D4
8 SO TC 44 D7 D3
9 SI SO 43 D6 D2
10 RC SI 42 D5 D1
11 Vcc RC 41 D4 D0
12 NC Vcc 40 D3 GND
13 TA 0 NC 39 D2 CLK
14 TB 0 NC 38 D1 IE1
15 TC 0 TAO 37 D0 IE0
16 TD 0 TBO 36 Vss IRQ
17 XTAL 1 TCO 35 CLK NC
18 XTAL 2 TDO 34 IEI NC
19 TA 1 XTAL1 33 IEO NC
20 TB 1 XTAL2 32 INTR IO7
21 RESET NC 31 RR IO6
22 I0 TAI 30 TR IO5
23 I1 TBI 29 17 IO4
24 I2 Reset 28 16 IO3
25 13 IO0 26 14 IO1
26 14 IO1 27 15 IO2
Kommen wir nun zu den Funktionsbaugruppen des MFP-Bausteins:
A smal english description of the MFP Chip follows.
MC68901 Multi-Function Peripheral Chip
Jeff Rigby/SOTA Computers
The 68901 is a very inexpensive very powerful multi-function chip.
In the ST it is responsible for the interrupt generation of the busy
line on the printer port, the interrupt signal from the hard drive
port and the prin- ter port, Midi port, keyboard, and RS-232 port as
well as the entire RS - 232 receive, transmit and controll lines (16
levels of interrupt ). In ad- dition, the MFP can be daisy chained ( a
second 68901 can be added allo - wing the interrupt levels to be
chained ). All this in a chip with a re - tail cost of about $12.00.
How it works; the 68000 CPU has 7 levels of interrupt, one of
those levels points to the 68901 MFP, when the CPU is told that the
MFP needs servi - ceing, the address of the service routine is given
controll, it addresses $fffffa00 which the glue chip decodes and sends
a low on the chip select pin 48 of the MFP, then the routine sends an
address to the lower 5 lines of the address bus to select a register
in the MFP and the routine, depen- ding on what it needs to do writes
or reads the registers in the chip.
The operating system has previously set the interrupt registers in
the MFP with the priorities the Interrupt lines I0-I7 and the internal
receive and transmit buffers require. The 68901 then talks directly to
the 68000 tel - ling it that one of it's interrupt's needs servicing,
giving the vector adress of the service routine, and this goes on
until all the 68901 inter- rupts are serviced then control is passed
back to the 68000 and the pro - cess starts all over again. If no
interrupts need servicing then control is passed back to the 68000
immediately.
I'll try to make this as non-technical as possible.
MFP tells the Glue chip that it needs servicing. Glue thinks and
says OK, I guess it is your turn. Glue tells CPU that a IRQ level is
pending. CPU to Glue " what level is it ". CPU to Glue tell
the MFP it's his turn. Glue tells MFP to go ahead -> CS on MFP goes
low MFP gives the CPU the vector for the needed routine The routine
services the MFP and clears the Interrupt register. Control is passed
back to the CPU and the next level down interrupt has a chance.
Maybe that was too simple, the 68901 does alot more than that and
I could spend all day and 30 screens to tell you about it.
Literature is available from Motorola on the MC68901, I believe
the 28 pa- ge technical booklet is #ADI-984, The great thing is that
we can add a se- cond RS-232 very cheaply by daisy chaining the IEI
and IEO pins on the 68901 and changing the vector addresses for the
service routines.
A few suggestions for standards in the ST upgrades.
As a hardware hacker, I am interested in other people's input on
this sub- ject. The great thing about PD software is that people build
upon the work of others and eventually the PD software can be better
than commercial software. I would like to see something like that
started on the technical side, if someone finds a flaw or a better way
to describe the 68901 please add it to this file and upload to CIS.
Jeff Rigby/SOTA Computers
Abbildung 1 - Atari MFP Chip
Introduction
The MK68901 MFP (Multi-Function Peripheral) is a combination of
many of the necessary peripheral functions in a microprocessor system.
Included are:
The MFP is a derivative of the MK3801, a Z80 family peripheral.
Interrupts
The General Purpose I/O-Interrupt Port (GPIP) provides eight I/O
lines that may be operated either as inputs or outputs under software
control. In addition, each line may generate an interrupt on either a
positive going edge or a negative going edge of the input signal.
The GPIP has three associated registers. One allows the programmer
to specify the Active Edge for each bit that will trigger an
interrupt. Another register specifies the Data Direction (input or
output) associated with each bit. The third register is the actual
data I/O register used to input or output data to the port. These
three registers are illustrated below.
General Purpose I/O Registers
Active Edge Register
Port 1 (AER) GPIP GPIP GPIP GPIP GPIP GPIP GPIP GPIP 1=Rising
7 6 5 4 3 2 1 0 0=Falling
Data Direction Register
Port 2 (DDR) GPIP GPIP GPIP GPIP GPIP GPIP GPIP GPIP 1=Output
7 6 5 4 3 2 1 0 0=Input
General Purpose I/O Register
Port 3 (GPIP) GPIP GPIP GPIP GPIP GPIP GPIP GPIP GPIP
7 6 5 4 3 2 1 0
The Active Edge Register (AER) allows each of the General Purpose
Interrupts to produce an interrupt on either a 1-0 transition or a 0-1
transition. Writing a zero to the appropriate bit of the AER causes
the associated input to produce an interrupt on the 1-0 transition,
while a 1 causes the interrupt on the 0-1 transition. The edge bit is
simply one input to an exclusive-or gate, with the other input coming
from the input buffer and the output going to a 1-0 transition
detector. Thus, depending upon the state of the input, writing the AER
can cause an interrupt-producing transition, which will cause an
interrupt on the associated channel, if that channnel is enabled. One
would than normally configure the AER before enabling interrupts via
IERA an IERB. Note: changing the edge bit, with the interrupt enabled,
may cause an interrupt on that channel.
The Data Direction Register (DDR) is used to define I0-I7 as input
or as outputs on a bit by bit basis. Writing a zero into a bit of the
DDR causes the corresponding Interrupt I/O pin to be a Hi-Z Input.
Writing a one into a bit of the DDR causes the corresponding pin to be
configured as a push-pull output. When data is written into the GPIP,
those pins defined as inputs will remain in the Hi-Z state while those
pins defines as outputs will assume the state (high or low) of their
corresponding bit in the PIP. When the GPIP is read, the data read
will come directly from the corresponding bit of the GPIP register for
all pins defines as output, while the data read on all pins defined as
inputs will come from the input buffers.
Each individual functions in the MK68901 is provided with a unique
interrupt vector that is presented to the system during the interrupt
acknowledge cycle. The interrupt vector returned during the interrrupt
acknowledge cycle is shown below.
Interrupt Vector
V7 V6 V5 V4 V3 V2 V1 V0
\-----------------/\----------------/
| |
| ------------ Vector bits 3-0 supplied
| by the MFP based upon the interrupting
| channel.
|
------------------------------- 4 most significant bits. Copied
from the vector register.
Vector Register
V7 V6 V5 V4 S * * *
\-----------------/ |
| |
| ------------------- S In-Service Register Enable
|
------------------------------- Upper 4 bits of the Vector Register
Written into by the user.
There are 16 vector addresses generated internally by the MK68901, one for
each of the 16 interrupt channels.
The Interrupt Control Registers provide control of interrupt
processing for all I/O facilities of the MK68901. These registers
allow the programmer to enable or disable any or all of the 16
interrupts, providing masking for any interrupts, and provide access
to the pending and in-service status of the interrupts. Optional
end-of-interrupt modes are availble under software control.
Interrupt Control Registers
Interrupt Enable Registers
Port 3 (IERA) GPIP GPIP TIMER RCV RCV XMIT XMIT TIMER
7 6 A Full Err Empty Err B
Port 4 (IERB) GPIP GPIP TIMER TIMER GPIP GPIP GPIP GPIP
5 4 C D 3 2 1 0
Interrupt Pending Registers
Port 5 (IPRA) GPIP GPIP TIMER RCV RCV XMIT XMIT TIMER
7 6 A Full Err Empty Err B
Port 6 (IPRB) GPIP GPIP TIMER TIMER GPIP GPIP GPIP GPIP
5 4 C D 3 2 1 0
Writing 0: Clear
Writing 1: Unchanged
Interrupt In-Service Registers
Port 7 (ISRA) GPIP GPIP TIMER RCV RCV XMIT XMIT TIMER
7 6 A Full Err Empty Err B
Port 8 (ISRB) GPIP GPIP TIMER TIMER GPIP GPIP GPIP GPIP
5 4 C D 3 2 1 0
Interrupt Mask Registers
Port 9 (IMRA) GPIP GPIP TIMER RCV RCV XMIT XMIT TIMER
7 6 A Full Err Empty Err B
Port A (IMRB) GPIP GPIP TIMER TIMER GPIP GPIP GPIP GPIP
5 4 C D 3 2 1 0
1: UnMasked 0: Masked
Interrupts may be either polled or vectored. Each channel may be
individually enabled or disabled by writing a one or a zero in the
appropriate bit of the Interrupt Enable Registers (IERA,IERB). When
disabled, an interrupt channel is completely inactive. Any internal or
external action which would normally produce an interrupt on that
channel is ignored and any pending interrupt on that channel will be
cleared by disabling that channel. Disabling and interrupt channel has
no effect on the corresponding bit in Interrupt in-Service Registers
(ISRA,ISRB); thus, if the In-Service Registers are used and an
interrupt is in service on that channel when the channel is disabled,
it will remain in service until cleared in the normal manner. IERA and
IERB are also readable.
When an interrupt is received on an enabled channel, its
corresponding bit in the pending register will be set. When that
channel is acknowledged it will pass its vector, and the corresponding
bit in the Interrupt Pending Register (IPRA or IPRB) will be cleared.
IPRA and IPRB are readable; thus by polling IPRA and IPRB, it can be
determind whether a channel has a pending interrupt. IPRA and IPRB are
also writeable and a pending interrupt can be cleared without going
through the acknowledge sequence by writing a zero to the appropriate
bit. This allows any one bit to be cleared, without altering any other
bits, simply by writing all ones except for the bit position to be
cleared on IPRA or IPRB. Thus a full polled interrupt scheme is
possible. Note: writing a one to IPRA, IPRB has no effect on the
interrupt pending register.
The interrupt mask registers (IMRA and IMRB) may be used to block
a channel from making an interrupt request. Writing a zero into the
corresponding bit of the mask register will still allow the channel to
receive and interrupt and latch it into its pending bit (if that
channel is enabled), but will prevent that channel from making an
interrupt request. If that channel is causing an interrupt request at
the time the corresponding bit in the mask register is cleared, the
request will cease. If no other channel is making a request, INTR will
go inactive. If the mask bit is re-enabled, any pending interrupt is
now free to resume its request unless blocked by a higher priority
request for service. IMRA and iMRB are also readable.
A conceptual circuit of an interrupt
Edge Enable Mask
Register Register Register S-Bit
| | | |
| | ----|---\ --|---\ |------------|
| o-----|---\ |-----------| | |---o---------| ||S Interrupt |
---\\--\ | | ||S Pending Q|------|---/ | --|---/ | Service |
|| |---|-----|---/ | R | | | |------------|
I7-------//--/ | |-----------| | |
| | Interrupt |
----- /---\ Request |
\ / | | |
\ / /---\ |
o | | |
| | | |
------------------ -----------------------------o------ Pass Vector
Each interrupt channel responds with a discrete 8-bit vector when
acknowledged. The upper four bits of the vector are set by writing the
upper four bits of the VR. The four low order bits (bit 3-bit 0) are
generated by the interrupt channel.
To acknowledge an interrupt, IACK goes low, the IEI input must go
low (or be tied low) and the MK68901 MFP must have acknowledgeable
interrupt pending. The daisy chaining capability requires that all
parts in a chain have a command IACK. When the command IACK goes low
all parts freeze and prioritize interrupts in parallel. Then priority
is passed down the chain, via IEI and IEO, until a part which has a
pending interrupt is reached. The part with the pending interrupt,
passes a vector, does not propagate IEO, and generates DTACK.
Timers
There are four timers on the MK68901 MFP. Two of the timers (Timer
A and Timer B) are full function timers which can perform the basic
delay function and can also perform event counting, pulse width
measurement and waveform generation. The other two timers (Timer C and
Timer D) are delay timers only. One or both of these timers can be
used to supply the baud rate clocks for the USART. All timers are
prescaler/counter timers with a common independent clock input (XTAL1,
XTAL2). In addition, all timers have a time-out output function that
toggles each time the timer times out.
The four timers are programmed via three Timer Control Registers
and four Timer Data Registers. Timers A and B are controlled bu the
control registers TACR and TBCR, respectively, and by the data
registers TADR and TBDR. Timers C and D are controlled by the control
register TCDCR and two data registers TCDR and TDDR. Bits in the
control registers allow the selection of operational mode, prescale,
and control, while data registers are used to read the timer or write
into the time constant register. Timer A and B input pins, TAI and
TBI, are used for the event and pulse width modes for timers A and B.
Timer Data Registers (A,B,C and D)
Port F (TADR) D7 D6 D5 D4 D3 D2 D1 D0
Port 10 (TBDR) D7 D6 D5 D4 D3 D2 D1 D0
Port 11 (TCDR) D7 D6 D5 D4 D3 D2 D1 D0
Port 12 (TDDR) D7 D6 D5 D4 D3 D2 D1 D0
Timer A and B Control Register
Port C (TACR) * * * Reset AC3 AC2 AC1 AC0
Port D (TBCR) * * * Reset BC3 BC2 BC1 BC0
C3 C2 C1 C0
0 0 0 0 Timer Stopped
0 0 0 1 Delay Mode, /4 Prescale
0 0 1 0 Delay Mode, /10 Prescale
0 0 1 1 Delay Mode, /16 Prescale
0 1 0 0 Delay Mode, /50 Prescale
0 1 0 1 Delay Mode, /64 Prescale
0 1 1 0 Delay Mode, /100 Prescale
0 1 1 1 Delay Mode, /200 Prescale
1 0 0 0 Event Count Mode
1 0 0 1 Pulse Width Mode, /4 Prescale
1 0 1 0 Pulse Width Mode, /10 Prescale
1 0 1 1 Pulse Width Mode, /16 Prescale
1 1 0 0 Pulse Width Mode, /50 Prescale
1 1 0 1 Pulse Width Mode, /64 Prescale
1 1 1 0 Pulse Width Mode, /100 Prescale
1 1 1 1 Pulse Width Mode, /200 Prescale
Timer C and D Control Register
Port E (TCDCR) * CC2 CC1 CC0 * DC2 DC1 DC0
C2 C1 C0
0 0 0 Timer Stopped
0 0 1 Delay Mode, /4 Prescale
0 1 0 Delay Mode, /10 Prescale
0 1 1 Delay Mode, /16 Prescale
1 0 0 Delay Mode, /50 Prescale
1 0 1 Delay Mode, /64 Prescale
1 1 0 Delay Mode, /100 Prescale
1 1 1 Delay Mode, /200 Prescale
With the timer stopped, no counting can occur. The timer contents
will remain unaltered while the timer is stopped (unless reloaded by
writing the Timer Data Register), but any residual count in the
prescaler will be lost.
In the delay mode, the prescaler is always active. A count pulse
will be applied to the main timer unit each time the prescribed number
of timer clock cycles has elapsed. Thus, if the prescaler is
programmed to divide by ten, a count pulse will be applied to the main
counter every ten cycles of the timer clock.
Each time a count pulse is applied to the main counter, it will
decrement its contents. The main counter is initially loaded by
writing to the Timer Data Register. Each count pulse will cause the
current count to decrement. When the timer has decremented down to
'01', the next count pulse will not cause it to decrement to '00'.
Instead the next count pulse will cause the timer to be reloaded from
the Timer Data Register. Additionally, a 'Time Out' pulse will be
produced. This Time Out pulse is coupled to the timer interrupt
channel, and, if that channel is enabled an interrupt will be
produced. The Time Out pulse is also coupled to the timer output pin
and will cause the pin to change states. The output will remain in
this new state until the next Time Out pulse occurs. Thus the output
will complete one full cycle each two Time Out pulses.
If, for example, the prescaler were programmed to divide by ten,
and the Timer Data Register were loaded will 100(decimal), the main
counter would decrement once for every ten cycles of the timer clock.
A Time Out pulse will occur(hence an interrupt if that channel is
enabled) every 1000 cycles of the timer clock, and the timer output
will complete one full cycle every 2000 cycles of the timer clock.
The main counter is an 8-bit binary down counter. If may be read
at any time by reading the Timer Data Register. The information read
is the information last clocked into the timer read register when the
DS pin had last gone high prior to the current read cycle. When
written, data is loaded into the Timer Data Register, and the main
counter, if the timer is stopped. If the Timer Data Register is
written while the timer is running, the new word is not loaded into
the timer until it counts through H01. However, if the timer is
written while it is counting through H01, an indeterminate value will
be written into the time constant register. This may be circumvented
by ensuring that the daata register is not written when the count is
H01.
If the main counter is loaded with 01, a Time Out Pulse will occur
every time the prescaler presents a count pulse to the main counter.
If loaded with 00, a Time Out pulse will occur after every 256 count
pulses.
Changing the prescale value with the timer running can cause the
first Time Out pulse to occur at an indeterminate time, (no less than
one nor more than 200 timer clock cycles times the number in the time
constant register), but subsequent Time Out pulses will then occur at
the correct interval.
In addition to the delay mode described above, Timers A and B can
also function in Pulse Width Measurement mode or in the Event Count
mode. In either of these two modes, an auxilary count signal is
required. The auxilary control input for Timer A is TAI, and for Timer
B, TBI is used. The interrupt channels associated with I4 and I3 are
used for TAI and TBI, respectively, in Pulse Width mode.
The pulse width measurement mode functions much like the delay
mode. However, in this mode, the auxiliary control signal on TAI or
TBI acts as an enable to the timer. When the control signal on TAI or
TBI is inactive, the timer will be stopped. When it is active, the
prescaler and main counter are allowed to run. Thus the width of the
active pulse on TAI or TBI is determined by the number of timer counts
which occur while the pulse allows the timer to run. The active state
of the signal on TAI or TBI is dependent upon the associated Interrupt
Channels edge bit (GPIP4 for TAI and GPIP3 for TBI, see Active Edge
Register). If the edge bit associated with the TAI or TBI input is a
one, it will be active high, thus the timer will be allowed to run
when the input is at a high level. If the edge bit is a zero, the TAI
or TBI input will be active low. As previously stated, the interrupt
channel (I3 or I4) associated with the input still functions when the
timer is used in the pulse width measurement mode. However, if the
timer is programmed for the pulse width measurement mode, the
interrupt caused by transitions on the associated TAI or TBI input
will occur on the opposite transition.
A conceptual circuit of the MFP timer in the pulse width
measurement mode
|-----|
| TAI |
|-----|
|
-----------|---\
Timer A | |----
Pulse Width Mode ------------o----------|---/ |
| |---\---\ |-----------|
| | |-----| Interrupt |
|----| | |\ |---/---/ | Channel |
| I4 |-------| ----| o----|---\ | |-----------|
|----| | |/ | |----
------------------|---/
------------------|---\
|----| | |\ | |----
| I3 |-------| ----| o----|---/ |
|----| | |/ |---\---\ |-----------|
| | |-----| Interrupt |
Timer B | |---/---/ | Channel |
Pulse Width Mode ------------o----------|---\ | |-----------|
| |----
-----------|---/
|
|-----|
| TBI |
|-----|
For example, if the edge bit associated with the TAI input
(AER-GPIP 4) is a one, an interrupt would normally be generated on the
0-1 transition of the I4 input signal. If the timer associated with
this input (Timer A) is placed in the pulse width measurement mode,
the interrupt will occur on the 1-0 transition of the TAI signal
instead. Because the edge bit (AER-GPIP4) is a one, Timer A will be
allowed to count while the input is high. When the TAI input makes the
high to low transition, Timer A will stop, and it is at this point
that the interrupt will occur (assuming that the channel is enabled).
This allows the interrupt to signal the CPU that the pulse being
measured has terminated this Timer A may now be read to determine the
pulse width. (Again note that I3 and I4 may still be used for I/O when
the timer is in the pulse width measurement mode). If Timer A is
re-programmed for another mode, interrupts will again occur on the
transition, as normally defined by the edge bit. Note that, like
changing the edge bit, placing the timer into or taking it out of
pulse width mode can produce a transition on the signal to the
interrupt channel and may cause an interrupt. If measuring consecutive
pulses, it is obvious that one must read the contents of the timer and
reinitalize the main counter by writing to the timer data register. If
the timer data register is written while the pulse is going to the
active state, the write operation may result in an indeterminate value
being written into the main counter. If the timer is written after the
pulse goes active, the timer counts from the previous contents, and
when it counts through H01, the correct value is written into the
timer. The pulse width then includes counts from before the timer was
reloaded.
In the event count mode, the prescaler is disabled. Each time the
control input on TAI or TBI makes an active transition as defined by
the associated Interrupt Channel's edge bit, a count pulse will be
generated, and the main counter will decrement. In all other respects,
the timer functions as previously described. Altering the edge bit
while the timer is in the event count mode can produce a count pulse.
The interrupt channel associated with the input (I3 for TBI or I4 for
TAI) is allowed to function normally. To count transitions reliably,
the input must remain in each state (1/0) for a length of time equal
to four perioids of the timer clock; thus signals of a frequency up to
one fourth of the timer clock can be counted.
The manner in which the timer output pins toggle states has
previously been described. All timer outputs will be forced low by a
device RESET. The output associated with Timers A and B will toggle on
each Time Out pulse regardless of the mode the timers are programmed
to. In addition, the outputs from Timers A and Timers B can be forced
low at any time by writing a 1 to the reset location in TACR and TBCR,
respectively. The output will be forced to the low state during the
WRITE operation, and at the conclusion of the operation, the output
will again be free to toggle each time a Time Out pulse occurs. This
feature will allow waveform generation.
During reset, the Timer Data Registers and the main counters are
not reset. Also, if using the reset option on Timers A or B, one must
make sure to keep the other bits in the correct state so as not to
affect the operation of Timers A and B.
Copyright © Robert Schaffner (doit@doitarchive.de) Letzte Aktualisierung am 23. Mai 2004 |
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