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8.1.3 WD1772 FDC
WD1772 Floppy Disk Controller
Hier finden Sie einige wenige mühsam zusammengesuchte
Informationen zum WD1772 Floppy Controller. Möglicherweise fehlt
hier eine Menge!
Der WD1772 kann mit Stepraten von 2, 3, 5 und 6 msec arbeiten.
Alle Ausgangs Pin des WD1772 können einen TTL-Eingang bedienen.
Das Prozessor-Interface ist ein 8-Bit Bidirektionaler Datenbus
für Daten und Kommandos.
Beschreibung
Wenn ein Datentransfer zwischen dem WD1772 und der CPU stattfindet
muß die Device Adresse anliegen und CS Low werden. Die
Adressbits A1 und A0 zusammen mit dem R/W Signal erlauben eine Lese-
oder Schreiboperation in die Chipregister nach der folgenden Tabelle:
During Direct Memory Access (DMA) types of data transfers between the Data Register of the WD1772 and the processor, the Data ReQuest (DRQ) output is used in Data Transfer control. This signal also appears as status bit 1 during Read and Write operations. On Disk Read operations the Data Request is activated (set high) when an assembled serial input byte is transferred in parallel to the Data Register. This bit is cleared when the Data Register is read by the processor. If the Data Register is read after one or more characters are lost, by having new data transferred to the register prior to processor readout, the Lost Data bit is set in the Status Register. The read operation continues until the end of sector is reached. On Disk Write operations the Data ReQuest is activated when the Data Registers its contents to the Data Shift Register and requires a new data byte. It is reset when the Data Register is loaded with new data by the processor. If new data is not loaded at the time serial byte is required by the Floppy Disk, a byte of zeroes is written on the diskette and the Lost Data bit is set in the Status Register. At the completion of every command an INTRQ is generated. INTRQ is reset by either reading the status register or by loading the command register with a new command. In addition INTRQ is generated if a Force Interrupt command condition is met. The WD1772 has two modes of operation according to the state of notDDEN (pin 26). When DDEN = 1, single density is selected. In either case, the CLK input (pin 18) is at 8 MHz. GENERAL DISK READ OPERATIONS Sector lengths of 128, 256, 512 or 1024 bytes are obtainable in either FM or MFM formats. For FM formats, DDEN should be placed to logical "1". For MFM formats, notDDEN should be placed to logic "0". Sector lengths are determined at format time by hte fourth byte in the ID field.
The number of sectors per track as far as the WD1772 is concerned can be from 1 to 255 sectors. The number of tracks as far as the WD1772 is concerned is from 0 to 255 tracks. GENERAL DISK WRITE OPERATION
Writing is inhibited when the notWP (Write Protect) input is a logic low, in which case any Write command is immediately terminated, an interrupt generated and the Write Protection status bit is set. For Write operations, the WD1772 provides Write Gate (pin 21) to enable a write condition and Write Data (pin 22) which consists of a series of active high pulses. These pulses contain both Clock and Data information in FM or MFM. Write Data provides the unique missing clock patterns for recording Address Marks. RESTORE (SEEK TRACK 0)
SEEK
STEP
STEP-IN
Abbildung 1 - Atari WD 1772 Floppy Controller
WD1770/1772 5 1/4 " Floppy Disk Controller/Formatter
DESCRIPTION
The WD1770 is a low cost version of the FD179x Floppy Disk
Controller/Formatter. It is compatible with the 179x, but has a
built-in digital data separator and write precompensation circuits. A
single read line (notRD, pin 19) is the only input required to recover
serial FM or MFM data from the disk drive. The device has been
specifically designed for control of 5 1/4 " floppy disk drives
with data rates of 125 Kbits/sec (single density) and 250 Kbits/sec
(double density). In addition write precompensation of 125 Nsec from
nominal can be enabled at any point through simple software commands.
Another programmable feature, Motor On, has been incorporated to
enable the spindle motor prior to operating a selected drive.
Two versions of the WD1770 are available. The standard version is
compatible with the 179x stepping rates, while the WD1772 offers
stepping rates of 2, 3, 5 and 6 msec.
The processor interface consists of an 8-bit bidirectional bus for
transfer of status, data and commands. All host communication with the
drive occurs through these data lines. They are capable of driving one
standard TTL load or three "LS" loads.
+------+
notCS 1 28 INTRQ
R/notW 2 27 DRQ
A0 3 26 notDDEN
A1 4 25 notWPRT
DAL0 5 24 notIP
DAL1 6 1772 23 notTR00
DAL2 7 FDC 22 WD
DAL3 8 21 WG
DAL4 9 20 MO
DAL5 10 19 notRD
DAL6 11 18 CLK
DAL7 12 17 DIREC
notMR 13 16 STEP
GND 14 15 Vcc
+------+
ARCHITECTURE
Data Shift Register - This 8-bit register assembles serial data
from the Read Data input (notRD) during Read operations and transfers
serial data to the Write Data output during write operations.
Data Register - This 8-bit register is used as a holding register
during Disk read and Write operations. In Disk Read operations the
assembled data byte is transferred in parallel to the Data register
from the Data Shift Register. In Disk Write operations information is
transferred in parallel from the the Data Register to the Data Shift
Register.
When executing the Seek command the Data Register holds the
address of the desired Track position. This register is loaded from
the DAL and gated into the DAL under processor control.
Track Register - This 8-bit register holds the track number of the
current Read/Write hed position. It is incremented by one every time
the head is stepped in and decremented by one when the head is stepped
out (towards track 00). The contents of the register are compared with
the recorded track number in the ID field during disk Read, Write and
Verify operations. The track register can be loaded from or
transferred to the DAL. This register should not be loaded when the
device is busy.
Sector Register (SR) - This 8-bit register holds address of the
desired sector postition. The contents of the register are compared
with the recorded sector number in the ID field during disk Read or
Write operations. The Sector Register contents can be loaded from or
transferred to the DAL. This register should not be loaded when the
device is busy.
Command Register (CR) - This 8-bit register holds the command
presently being executed. This register should not be loaded when the
device is busy unless the new command is a force interrupt. The
command register can be loaded from the DAL, but not read into the
DAL.
Status Register (STR) - This 8-bit register holds device Status
information. The meaning of the status bits is a function of the type
of command previously executed. This register can be read into the
DAL, but not loaded from the DAL.
CRC Logic - This logic is used to check or to generate the 16-bit
Cyclic Redundancy Check (CRC). The polynominal is:
g(x)=x^16+x^12+x^5+1 The CRC includes all information starting with
the address mark and up to the CRC characters. The CRC register is
preset to ones prior to data being shifted through the circuit.
Arithmetic/Logic Unit (ALU) - The ALU is a serial comperator,
incrementer and decrementer and is used for register modification and
comparisons with the disk recorded ID field.
Timing and Control - All computer and floppy disk interface
controls are generated through this logic. The internal device timing
is generated from an external crystal clock. The FD1770 has two
different modes of operation according to the state of notDDEN. When
notDDEN = 0., double density is enabled. When notDDEN = 1, single
density is enabled.
AM Detector - The address mark detector detects ID, data and index
address marks during read and write operations.
Data Separator - A digital data separator consisting of a nng
shift register and data window detection logic provides read data and
a recovery clock to the AM detector.
PROCESSOR INTERFACE
The interface to the processor is accomplished through the eight
Data Access Lines (DAL) and associated control signals. The DAL are
used to transfer data, Status and Control words out of, or into the
WD1770. The DAL are three state buffers that are enabled as output
drivers when Chip Select (notCS) and R/notW = 1 are active or act as
input receivers when notCS and R/notW = 0 are active.
When transfer of data with the Floppy Disk Controller is required
by the host processor, the device address is decoded and notCS is made
low. The address bits A1 and A0, combined with the signal R/notW
during a Read operation or Write operation are interpreted as selecing
the following registers:
+----+----+-----------------+------------------+
! A1 ! A0 ! READ ! WRITE !
+----+----+-----------------+------------------+
! 0 ! 0 ! Status Register ! Command Register !
! 0 ! 1 ! Track register ! Track Register !
! 1 ! 0 ! Sector register ! Sector Register !
! 1 ! 1 ! Data Register ! Data Register !
+----+----+-----------------+------------------+
During Direct Memory Access (DMA) types of data transfers between
the Data Register of the WD1770 and the processor, the Data ReQuest
(DRQ) output is used in Data Transfer control. This signal also
appears as status bit 1 during Read and Write operations.
On Disk Read operations the Data Request is activated (set high)
when an assembled serial input byte is transferred in parallel to the
Data Register. This bit is cleared when the Data Register is read by
the processor. If the Data Register is read after one or more
characters are lost, by having new data transferred to the register
prior to processor readout, the Lost Data bit is set in the Status
Register. The read operation continues until the end of sector is
reached.
On Disk Write operations the Data ReQuest is activated when the
Data Registers its contents to the Data Shift Register and requires a
new data byte. It is reset when the Data Register is loaded with new
data by the processor. If new data is not loaded at the time serial
byte is required by the Floppy Disk, a byte of zeroes is written on
the diskette and the Lost Data bit is set in the Status Register.
At the completion of every command an INTRQ is generated. INTRQ is
reset by either reading the status register or by loading the command
register with a new command. In addition INTRQ is generated if a Force
Interrupt command condition is met.
The WD1770 has two modes of operation according to the state of
notDDEN (pin 26). When notDDEN = 1, single density is selected. In
either case, the CLK input (pin 18) is at 8 MHz.
GENERAL DISK READ OPERATIONS
Sector lengths of 128, 256, 512 or 1024 bytes are obtainable in
either FM or MFM formats. For FM formats, notDDEN should be placed to
logical "1". For MFM formats, notDDEN should be placed to
logic "0". Sector lengths are determined at format time by
hte fourth byte in the ID field.
+---------------------------------+
! SECTOR LENGTH TABLE !
+---------------+-----------------+
! SECTOR LENGTH ! NUMBER OF BYTES !
! FIELD (HEX) ! IN SECTOR (DEC) !
+---------------+-----------------+
! 00 ! 128 !
! 01 ! 256 !
! 02 ! 512 !
! 03 ! 1024 !
+---------------+-----------------+
The number of sectors per track as far as the WD1770 is concerned
can be from 1 to 255 sectors. The number of tracks as far as the
WD1770 is concerned is from 0 to 255 tracks.
GENERAL DISK WRITE OPERATION
When writing is to take place on the diskette, the Write Gate (WG)
output is activated, allowing current to flow into the Read/Write
head. As a precaution to erroneous writing the first data must be
loaded into the Data Register in response to a Data ReQuest from the
device before the Write Gate signal can be activated.
Writing is inhibited when the notWP (Write Protect) input is a
logic low, in which case any Write command is immediately terminated,
an interrupt generated and the Write Protection status bit is set.
For Write operations, the WD1770 provides Write Gate (pin 21) to
enable a write condition and Write Data (pin 22) which consists of a
series of active high pulses. These pulses contain both Clock and Data
information in FM or MFM. Write Data provides the unique missing clock
patterns for recording Address Marks.
The Precomp Enable bit in Write commands allow automatic Write
Precompensation to take place. The outgoing Write Data Stream is
delayed or advanced according to the following table:
+----------+--------+------+
! PATTERN ! MFM ! FM !
+----------+--------+------+
! x 1 1 0 ! Early ! N/A !
! x 0 1 1 ! Late ! N/A !
! 0 0 0 1 ! Early ! N/A !
! 1 0 0 0 ! Late ! N/A !
+----------+--------+------+
^ ^ ^ ^
! ! ! +- Next bit to be sent
! ! +--- Current bit sending
+-+----- Previous bits sent
Precompensation is typically enabled on the innermost tracks where
bit shifts usually occur and bit density is at its maximum.
COMMAND DESCRIPTION
De WD1770 will accept eleven commands. Command words should only
be loaded in the Command Register when the Busy status bit is off
(Status bit 0). The one exception is the force interrupt command.
Whenever a command is being executed, the Busy status bit is set. When
a command is completed, an interrupt is generated and the Busy status
bit is reset. The status register indicates whether the completed
command encountered an error or was fault free. For ease of
discussion, commands are divided into four types. Commands and types
are summarized in tale 1.
COMMAND SUMMARY
+------+----------+-------------------------+
! ! ! BITS !
! TYPE ! COMMAND ! 7 6 5 4 3 2 1 0 !
+------+----------+-------------------------+
! 1 ! Restore ! 0 0 0 0 h v r1 r0 !
! 1 ! Seek ! 0 0 0 1 h v r1 r0 !
! 1 ! Step ! 0 0 1 u h v r1 r0 !
! 1 ! Step-in ! 0 1 0 u h v r1 r0 !
! 1 ! Step-out ! 0 1 1 u h v r1 r0 !
! 2 ! Rd sectr ! 1 0 0 m h E 0 0 !
! 2 ! Wt sectr ! 1 0 1 m h E P a0 !
! 3 ! Rd addr ! 1 1 0 0 h E 0 0 !
! 3 ! Rd track ! 1 1 1 0 h E 0 0 !
! 3 ! Wt track ! 1 1 1 1 h E P 0 !
! 4 ! Forc int ! 1 1 0 1 i3 i2 i1 i0 !
+------+----------+-------------------------+
FLAG SUMMARY
+-------------------------------------------+
! TYPE 1 COMMANDS !
+-------------------------------------------+
! h = Motor on Flag (bit 3) !
! h = 0 Enable spin-up Sequence !
! h = 1 Disable spin-up Sequemce !
! !
! v = Verify Flag (bit 2) !
! v = 0 No verify !
! v = 1 Verify on destn track !
! !
! r1, r0 = Stepping rate (bits 1, 0) !
! r1 r0 WD1770 WD1772 !
! 0 0 6 ms 2 ms !
! 0 1 12 ms 3 ms !
! 1 0 20 ms 5 ms !
! 1 1 30 ms 6 ms !
! !
! u = Update Flag (bit 4) !
! u = 0 No update !
! u = 1 Update Track Register !
+-------------------------------------------+
+-------------------------------------------+
! TYPE 2 & 3 COMMANDS !
+-------------------------------------------+
! m = Multiple Sector Flag (bit 4) !
! m = 0 Single sector !
! m = 1 Multiple sector !
! !
! a0= Data Address Mark (bit 0) !
! a0= 0 Write normal Data Mark !
! a0= 1 Write Deleted Data Mark !
! !
! E = 30ms Settling Delay (bit 2) !
! E = 0 No delay !
! E = 1 Add 30ms Delay !
! !
! P = Write Precompensation (bit 1) !
! P = 0 Enable Write Precomp !
! P = 1 Disable Write Precomp !
+-------------------------------------------+
+-------------------------------------------+
! TYPE 4 COMMANDS !
+-------------------------------------------+
! i3-i0 Interrupt condition (bit 3-0) !
! i0= 1 Don't care !
! i1= 1 Don't care !
! i2= 1 Interrupt on index pulse !
! i3= 1 Immediate interrupt !
! 13-i0 = 0 Terminate without interrupt !
+-------------------------------------------+
TYPE 1 COMMANDS
The type 1 commands include the Restore, Seek, Step, Step-in and
Step-out commands. Each of the Type 1 commands contains a rate field
(r0, r1), which determines the stepping motor rate.
A 4uS (MFM) of 8uS (FM) pulse is provided as an output to the
drive. For every step pulse issued, the drive moves one track location
in a direction determined by the direction output. The chip will step
the drive in the same direction it last stepped, unless the command
changes the direction.
The direction signal is active high when stepping in and low when
stepping out. The Direction signal is valid 24uS before the first
stepping pulse is generated.
After the last directional step an additional 30 milliseconds of
head settling time takes if the verify flag is set in type 1 commands.
There is also a 30mS head settling time if the E flag is set in any
Type 2 or 3 command.
When a Seek, Step or Restore command is executed, an optional
verification of Read/Write head position can be performed by setting
bit 2 (V=1) in the command word to a logic "1". The
verification operation begins at the end of the 30 millisecond
settling time after the head is loaded against the media. The track
number from the first encountered ID field is compared against the
contents of the Track Register. If the track numbers compare and the
ID field CRC is correct, the verify operations is complete and an
INTRQ is generated with no errors. If there is a match but not a valid
CRC, the CRC error status bit is set (Status bit 3) and the next
encountered ID field is read from the disk for the verification
operation.
The WD1770 must find an ID field with correct track number and
correct CRC within 5 revolutions of the media, otherwise the seek
error is set and an INTRQ is generated. If V=0 no verification is
performed.
All commands except the Force Interrupt command may be programmed
via the h Flag to delay for spindle motor startup time. If the h Flag
is set and the Motor On line (pin 20) is low when a command is
received, the WD1770 will force Motor On to a logic "1" and
wait 6 revolutions before executing the command. At 300rpm this
guarantees a one second spindle startup time. If after finishing the
command, the device remains idle for 10 revolutions, the Motor On line
will go back to a logic "0". If a command is issued while
Motor On is high, the command will execute immediately, defeating the
6 revolutions start up. This feature allows consecutive Read or Write
commands without waiting for motor start up each time; the WD1770
assumes the spindle motor is up to speed.
RESTORE (SEEK TRACK 0)
Upon receipt of this command, the Track 00 (notTR00) input is
sampled. If notTR00 is active low indicating the Read/Write head is
positioned over track 0, the Track register is loaded with zeroes and
an interrupt is generated. If notTR00 is not active low, stepping
pulses (pin 16) at a rate specified by the r1, r0 field are issued
until the notTR00 input is activated. At this time, the Track Register
is loaded with zeroes and an interrupt is generated. If the notTR00
input does not go active low after 255 stepping pulses, the WD1770
terminates operation, interrupts and sets the Seek error status bit,
providing the V flag is set. A verification als takes place if the V
flag is set. The h bit allows the Motor On option at the start of
command.
SEEK
This command assumes that the track register contains the track
number of the current position of the Read/Write head and the Data
Register contains the desired track number. The WD1770 will update the
Track Register and issue stepping pulses in the appropiate direction
until the contents of the Track Register are equal to the contents of
the Data Register (the desired Track location). A verification
operation takes place if the V flag is on. The h bit allows the Motor
On option at the start of the command. An interrupt is generated at
the completion of the command. Note: When using mutiple drives, the
track register must be updated for the drive selected before seeks are
issued.
STEP
STEP-IN
TYPE 2 COMMANDS
The type 2 commands are the read sector and write sector commands.
Prior to loading the type 2 command into the command register, the
computer must load the sector register with the desired sector number.
Upon receipt of the type 2 command, the busy status bit is set. If the
E flag is 1, the command will execute after 30ms delay.
When an ID field is located on the disk, the WD1770 compares the
track number on the ID field with the Track register. If there is not
a match, the next encountered ID field is read and a comparison is
again made. If there was a match, the Sector Number of the ID field is
compared with the Sector Register. If there is not a Sector match, the
next encountered ID field is read off the disk and comparisons again
made. If the ID field CRC is correct, the data field is then located
and will be either written into, or read from depending upon the
command. The WD1770 must find an ID field with a track number, sector
number and CRC within four revolutions of the disk, otherwise, the
Record not found status bit is set (status bit 4) and the command is
terminated with an interrupt (INTRQ).
Each of the type 2 commands contains an (m) flag which determines
if multiple records (sectors) are to be read or written, depending
upon the command. If m=0, a single record is read or written and an
interrupt is generated at the completion of the command. If m=1,
multiple records are read or written with the sector register
internally updated so that an address verification can occur on the
next record. The WD1770 will continue to read or write multiple
records and update the sector register in numerical ascending sequence
until the sector number exceeds the number of sectors on the track or
until the Force Interrupt command is loaded in the command register,
which terminates the command and generates an interrupt.
For example:
READ SECTOR
At the end of the Read operation, the type of Data Address Mark
encountered in the data field is recorded in the status register (bit
5) as shown:
+---------------------+
! STATUS BIT 5 !
+---------------------+
! 1 Deleted Data Mark !
! 0 Data Mark !
+---------------------+
WRITE SECTOR
+-----+---------------------------+
! a0 ! DATA ADDRESS MARK (BIT 0) !
+-----+---------------------------+
! 1 ! Deleted Data Mark !
! 0 ! Data Mark !
+-----+---------------------------+
The WD1770 then writes the data field and generates DRQ's to the
computer. If the DRQ is not serviced in time for conitinious writing
the lost data status bit is set and a byte of zeroes is written on the
disk. The command is not terminated. After the last data byte has been
written on the disk, the two byte CRC is computed internally and
written on the disk followed by one byte of logic ones in FM or MFM.
The WG output is then activated. INTRQ will set 24uSec (MFM) after the
last CRC byte is written. For partial sector writing, the proper
method is to write data and fill the balance with zeroes.
TYPE 3 COMMANDS
+-------+--------+--------+--------+-----+-----+
! TRACK ! SIDE ! SECTOR ! SECTOR ! CRC ! CRC !
! ADDR ! NUMBER ! ADDR ! LENGTH ! 1 ! 2 !
+-------+--------+--------+--------+-----+-----+
! 1 ! 2 ! 3 ! 4 ! 5 ! 6 !
+-------+--------+--------+--------+-----+-----+
Although the CRC characters are transferred to the computer, the
WD1770 checks for validity and the CRC error status bit if there is a
CRC error. The Track Address of the ID field is written into the
sector register so that a comparison can be made by the user. At the
end of the operation an interrupt is generated and the Busy status bit
is reset.
READ TRACK
The ID am, ID field, ID CRC bytes, DAM, data, and data CRC bytes
for each sector will be correct. The Gap Bytes may be read incorrectly
during write-splice time because of synchronization.
WRITE TRACK FORMATTING THE DISK
Upon receipt of the Write Track command, the Busy status bit is
set. Writing starts with the leading edge of the first encountered
index pulse and continues until the next index pulse, at which time
the interrupt is activated. The Data ReQuest is activated immediately
upon receiving the command, but writing will not start until after the
first byte has been loaded into the Data Register. If the DR has not
been loaded within 3 byte times, the operation is terminated making
the device not busy, the Lost Data Status bit is set, and the
interrupt is activated. If a byte is not present in the DR when
needed, a byte of zeroes is substituted.
This sequence continues from one index mark to the next index
mark. Normally, whatever data pattern appears in the data register is
written on the disk with a normal clock pattern. However, if the
WD1770 detects a data pattern of F5 through FE in the data register,
this is interpreted as data address marks with missing clocks or CRC
generation.
+--------------+-----------------------------+--------------------------+
! DATA PATTERN ! ! !
! IN DR (HEX) ! IN FM (not DDEN = 1) ! In MFM (notDDEN = 0) !
+--------------+-----------------------------+--------------------------+
! 00 thru F4 ! Wt 00 thru F4 with CLK = FF ! Wt 00 thru F4 in MFM !
! F5 ! Not Allowed ! Wt A1 in MFM, Preset CRC !
! F6 ! Not Allowed ! Wt C2 in MFM !
! F7 ! Generate 2 CRC bytes ! Generate 2 CRC bytes !
! F8 thru FB ! Wt F8-FB, Clk=C7,Preset CRC ! Wt F8 thru Fb, in MFM !
! FC ! Wt FC with Clk=D7 ! Wt FC in MFM !
! FD ! Wt FD with Clk=FF ! Wt FD in MFM !
! FE ! Wt FE, Clk=C7, Preset CRC ! Wt FE in MFM !
! FF ! Wt FF with Clk=FF ! Wt FF in MFM !
+--------------+-----------------------------+--------------------------+
The CRC generator is initialized when any data byte from F8 to FE
is about to be transferred from the DR to the DSR in FM or by receipt
of F5 in MFM. An F7 pattern will generate two CRC characters in FM or
MFM. As a consequence, the patterns F5 through FE must not appear in
the gaps, data fields or ID fields. Also, CRC's must be generated by
an F7 pattern.
Disks may be formatted in IBM 3740 or system 34 formats with
sector lengths of 128, 256, 512 or 1024 bytes.
TYPE 4 COMMANDS
The forced interrupt command is generally used to terminate a
multiple sector read or write command or to insure Type 1 status in
the status register. This command can be loaded into the command
register at any time. If there is a current command under execution
(Busy status bit set) the command will be terminated and the busy
status bit reset.
The lower four bits of the command determine the conditional
interrupt as follows:
i0 = Don't care
Wait 16uSec (double density) or 32uSec (single density) before
issuing a new command after issuing the forced interrupt. Loading a
new command sooner than this will nullify the forced interrupt.
Forced interrupt stops any command at the end of an internal
micro-instruction and generates INTRQ when the specified condition is
met. Forced interrupt will wait until ALU operations in progress are
complete (CRC calculations, compares, etc.).
STATUS REGISTER
The user has the option of reading the status register through
program control or using the DRQ with DMA or interrupt methods. When
the Data register is read the DRQ bit in the status register and the
DRQ line are automatically reset. A write to the Data Register also
causes both DRQ's to reset.
The busy bit is the status may be monitored with a user program to
determine when a command is complete, in lieu of using the INTRQ line.
When using the INTRQ, a busy status check is not recommended because a
read of the status register to determine the condition of busy will
reset the INTRQ line.
The format of the Status register is shown below:
+---------------------------------------+
! (BITS) !
! 7 6 5 4 3 2 1 0 !
+----+----+----+----+----+----+----+----+
! s7 ! s6 ! s5 ! s4 ! s3 ! s2 ! s1 ! s0 !
+----+----+----+----+----+----+----+----+
RECOMMENDED - 128 BYTES/SECTOR
Shown below is the recommended single-density format with 128
bytes/sector. In order to format a diskette, the user must issue the
Write Track command and load the data register with the following
values. For every byte to be written there is one Data Request.
+----------+------------------------------+
! NUMBER ! !
! OF BYTES ! HEX VALUE OF BYTE WRITTEN !
+----------+------------------------------+
! 40 ! FF (or 00) !
! +---- 1) ! !
! ! 6 ! 00 !
! ! 1 ! FE (ID field Address Mark) !
! ! 1 ! .. Track number !
! ! 1 ! .. Side number (0 or 1) !
! ! 1 ! .. Sector number (1 thru 1A) !
! ! 1 ! 00 (Sector length) !
! ! 1 ! F7 (2 CRC's written) !
! ! 11 ! FF (or 00) !
! ! 6 ! 00 !
! ! 1 ! FB (Data Address Mark) !
! ! 128 ! .. Data (IBM uses E5) !
! ! 1 ! F7 (2 CRC's written) !
! ! 10 ! FF (or 00) !
! +---- ! !
! 369 2) ! FF (or 00) !
+----------+------------------------------+
1) Write bracketed field 16 times.
256 BYTES/SECTOR
+----------+------------------------------+
! NUMBER ! !
! OF BYTES ! HEX VALUE OF BYTE WRITTEN !
+----------+------------------------------+
! 60 ! 4E !
! +---- 1) ! !
! ! 12 ! 00 !
! ! 3 ! F5 (Writes A1) !
! ! 1 ! FE (ID field Address Mark) !
! ! 1 ! .. Track number (0 thru 4C) !
! ! 1 ! .. Side number (0 or 1) !
! ! 1 ! .. Sector number (1 thru 1A) !
! ! 1 ! 01 (Sector length) !
! ! 1 ! F7 (2 CRC's written) !
! ! 22 ! 4E !
! ! 12 ! 00 !
! ! 3 ! F5 (Writes A1) !
! ! 1 ! FB (Data Address Mark) !
! ! 256 ! .. Data !
! ! 1 ! F7 (2 CRC's written) !
! ! 24 ! 4E !
! +---- ! !
! 668 2) ! 4E !
+----------+------------------------------+
1) Write bracketed field 16 times.
NON-STANDARD FORMATS
+----------+-------------+-------------+
! ! ! !
+----------+-------------+-------------+
! Gap 1 ! 16 bytes FF ! 32 bytes 4E !
! ! ! !
! Gap 2 ! 11 bytes FF ! 22 bytes 4E !
! ! ! !
! 1) ! 6 bytes 00 ! 12 bytes 00 !
! 1) ! ! 3 bytes A1 !
! ! ! !
! Gap 3 2) ! 10 bytes FF ! 24 bytes 4E !
! ! 4 bytes 00 ! 8 bytes 00 !
! ! 3 bytes A1 ! !
! ! ! !
! Gap 4 ! 16 bytes FF ! 16 bytes 4E !
+----------+-------------+-------------+
1) Byte counts must be exact
STATUS REGISTER DESCRIPTION
+-----+---------------+-------------------------------------------------+
!BIT ! NAME ! MEANING !
+-----+---------------+-------------------------------------------------+
! s7 ! MOTOR ON ! This bit reflects the status of the Motor On !
! ! ! output !
+-----+---------------+-------------------------------------------------+
! s6 ! WRITE PROTECT ! On read record: not used. On read track: not !
! ! ! used. On any write: it indicates a Write !
! ! ! Protect. This bit is reset when updated. !
+-----+---------------+-------------------------------------------------+
! s5 ! RECORD TYPE ! When set, this bit indicates that the Motor !
! ! SPIN-UP ! Spin-Up sequence has completed (6 revolutions) !
! ! ! on type 1 commands. Type 2 & 3 commands, this !
! ! ! bit indicates record Type. 0 = Data Mark, 1 = !
! ! ! Deleted Data Mark. !
+-----+---------------+-------------------------------------------------+
! s4 ! RECORD NOT ! When set, it indicates that the desired track, !
! ! FOUND (RNF) ! sector, or side were not found. This bit is !
! ! ! reset when updated. !
+-----+---------------+-------------------------------------------------+
! s3 ! CRC ERROR ! If s4 is set, an error is found in one or more !
! ! ! ID fields; otherwise it indicates error in data !
! ! ! field. This bit is reset when updated. !
+-----+---------------+-------------------------------------------------+
! s2 ! LOST DATA/ ! When set, it indicates the computer did not !
! ! TRACK 00 ! respond to DRQ in one byte time. This bit is !
! ! ! reset to zero when update. On type 1 commands, !
! ! ! this bit reflects the status of the TRACK 00 !
! ! ! pin. !
+-----+---------------+-------------------------------------------------+
! s1 ! DATA REQUEST/ ! This bit is a copy of the DRQ output. When set, !
! ! INDEX ! it indicates the DR is full on a Read Operation !
! ! ! or the DR is empty on a write operation. This !
! ! ! bit is reset to zero when updated. On type 1 !
! ! ! commands, this bit indicates the status of the !
! ! ! index pin. !
+-----+---------------+-------------------------------------------------+
! s0 ! BUSY ! When set, command is under execution. When !
! ! ! reset, no command is under execution. !
+-----+---------------+-------------------------------------------------+
TYPE 1 COMMAND FLOW
!
!
!-------<--------+
! !
+------+------+ !
/ has a type 1 \ no !
! command been !----->-+
\ /
+------+------+
!yes
+-----------+-----------+
! set busy, reset drq, !
! seek err, drq, intrq !
+-----------+-----------+
!
+--+--+
/ is \ no
! h = 0 !-------->-------+
\ ? / !
+--+--+ !
!yes !
+--------------+--------------+ !
! set MO, wait 6 index pulses ! !
+--------------+--------------+ !
! !
!-------<-------------+
!
+---+---+
/ is \ yes +-----------+
! command a !---->----! set !->-+
\step-in ?/ ! direction ! !
+---+---+ +-----------+ !
!no !
+----+----+ !
/ is \ yes +-----------+ !
! command a !--->----! reset !->-+
\ stepout ? / ! direction ! !
+----+----+ +-----------+ !
!no !
+---+---+ !
/ is \ yes !
! command a !----------------------->-+
\ step ? / !
+---+---+ !
!no !
+---+---+ +--+--+
/ is \ yes yes / is \
! command a !-----+ +-<---! u = 1 !
\ seek / ! ! \ ? /
+---+---+ ! ! +--+--+
restore !no ! ! !no
+-----+-----+ ! ! !
! FF to TR ! ! ! !
+-----+-----+ ! ! !
! ! ! !
+-----+-----+ ! ! !
! 0 to DR !-<---+ ! !
+-----+-----+ ! !
! ! !
+-+-+ +-+-+ +-+-+
! A ! ! B ! ! C !
\ / \ / \ /
+---+
! A !
\ /
!
+----------->---!
! !
! +-----+-----+
! ! DR to DSR !
! +-----+-----+
! !
! +--+--+
! / is \ yes
! ! TR =DSR !------------------->--------+
! \ ? / !
! +--+--+ !
! !no !
! +--+--+ !
! / is \ yes !
! ! DSR< TR !--------->----+ !
! +---+ \ ? / ! !
! ! B ! +--+--+ ! !
! \ / !no ! !
! ! +--------+--------+ +-------+-------+ !
! ! ! reset direction ! ! set direction ! !
! ! +--------+--------+ +-------+-------+ !
! ! ! ! !
! +------>----+------<------------+ !
! ! !
! +---+---+ !
! / is \ yes !
! ! direction !------>--+ !
! +---+ \ = 1 ? / ! !
! ! C ! +---+---+ ! !
! \ / !no ! !
! ! +----+----+ +----+----+ !
! ! ! inc TR ! ! dec TR ! !
! ! +----+----+ +----+----+ !
! ! ! ! !
! +------>----+-----<---------+ !
! ! !
! +----+----+ !
! / is head at\ yes +---------+ !
! ! track 0 and !--->-! 0 to TR !------->--+
! ! direction ! +---------+ !
! \ is 0 ? / !
! +----+----+ !
! !no !
! +-----------+-----------+ !
! ! issue one step pulse ! !
! +-----------+-----------+ !
! ! !
! +-----------+-----------+ !
! ! delay acc. to r1, r0 ! !
! +-----------+-----------+ !
! ! !
! +------+------+ !
! no / is command a \ yes !
+-<----! step, step-in !--------->-----+----<---+
\ or step-out ? / !
+-------------+ +-+-+
! D !
\ /
+---+
! D !
\ /
!
+-+-+
/ is \ no
! V = 1 !----->-----+
\ ? / !
+-+-+ /------+------\
!yes ! intrq, reset !
+------------->------------+ ! busy status !
! ! \-------------/
! +----+----+
! / have 6 \ yes
! ! index holes !------>--+
! \ passed ? / !
! +----+----+ /------+-------\
! !no ! intrq, reset !
! +----+----+ ! busy, set seek !
! no / has ID \ ! error !
+----<--------------! am been ! \--------------/
! \ detected /
! +----+----+
! !yes
! +----+----+
! no / does TR = \
+----<--------------! track nr of !
! \ ID field /
! +----+----+
! !yes
! +-------+ +----+----+
! ! SET ! yes / is there \
+-<---! CRC !-<---! a crc !
! ERROR ! \ CRC error /
+-------+ +----+----+
!no
+-----+-----+
! reset CRC !
+-----+-----+
!
/----+-----\
! intrq, !
! reset busy !
\----------/
TYPE 2
!
!
+---<-------+
! !
+---+---+ !
/ is type \ no !
! 2 command !--->-+
\ received/
+---+---+
!yes
+--------------+--------------+
! set busy, reset drq, !
! lost data, record not found !
! status bit 5 & 6 intrq !
+--------------+--------------+
!
+-+-+
no / is \
+--------<-----! h = 1 !
! \ ? /
! +-+-+
! !yes
! +--------+--------+
! ! set MO, wait !
! ! 6 index pulses !
! +--------+--------+
! !
+------------->----+
!
+-+-+
/ is \ no
! E = 1 !--->-+
\ ? / !
+-+-+ !
!yes !
+------>----+ !
! ! !
! +---+---+ !
! no / has \ !
+---+ +-<---! 30 mS ! !
! 4 ! \ expired / !
\ / +---+---+ !
! !yes !
+------------->----+----<----+
!
+---+---+
yes / is \
+----<-------! command !
! \ a write /
+--+--+ +---+---+
/ is \ !no
yes ! write ! no !
+---<----! protect !---------->--+
! \ on ? / !
! +--+--+ +-+-+
! ! 1 !
! /-----------------\ \ /
+---->-! intrq, reset busy !
! set write protect !
\-----------------/
+-+-+
! 1 !
\ /
!
+---------------------->---------+
! !
! +----+----+
! / have 5 \ yes
! ! index holes !--------->-----+
! \ passed ? / !
! +----+----+ /----------+----------\
! !no ! intrq, reset busy !
! +-----+-----+ ! set record not found !
! no / has ID am \ \---------------------/
+------<-----------------! been !
! \ detected ? /
! +-----+-----+
! !yes
! +-----+-----+
! no / does TR = \
+------<-----------------! track address !
! \ of ID field /
! +-----+-----+
! !yes
! +-----+-----+
! no / does SR = \
+-------<----------------! sector addr !
! \ of ID field /
! +-----+-----+
! !yes
! +------------+------------+
! ! bring in sector length !
! ! field, store in !
! ! internal register !
! +------------+------------+
! !
! +---+---+
! +--------------+ yes / is there\ no
+-<---! set CRC !-<---! a crc !----->--+
! status error ! \ error ? / !
+--------------+ +---+---+ +-----+-----+
! reset CRC !
+-----+-----+
!
+---+---+
yes / is \
+--<-----! command a !
! \ write ? /
! +---+---+
! !no
+-+-+ +-+-+
! 3 ! ! 2 ! read
\ / \ /
+-+-+ read sector
! 2 ! sequence
\ /
!
+----+----+
/ has data \ no
! AM occurred !---------->-------+
\ in time ? / !
+----+----+ !
!yes !
+----------+----------+ +-+-+
! put recording type ! ! 1 !
! in status reg bit 3 ! \ /
+----------+----------+
!
+-----<-------+
! !
+---+---+ !
/has first\ no !
! byte been !---->--+
! assembled !
\ in DSR ?/
+---+---+
!yes
+------>-----+
! !
! +----+----+
! ! set DRQ !
! +----+----+
! !
! +-----<-------+
! ! !
! +---+---+ !
! / has next\ no !
! ! byte been !---->--+
! ! assembled !
! \ in DSR ?/
! +---+---+
! !yes
! +----+----+
! / has DR \ no +--------+--------+
! ! been read !---->-! set data lost !
! \ DR = 0 ? / +--------+--------+
! +----+----+ !
! !yes !
! +-------<--------------+
! !
! +----+----+ +---+
! no / have all \ ! 5 !
+-<---! bytes been ! \ /
\ inputted / !
+----+----+ +------>--+
!yes ! !
+-+-+ ! +-+-+
/ CRC \ no ! / is \ no
! error !---->-+ ! M = 1 !---------->----+
\ ? / \ ? / !
+-+-+ +-+-+ !
!yes !yes !
! +------+------+ !
/------+------\ ! inc sectreg ! !
! intrq, reset ! +------+------+ !
! busy, set crc ! ! !
! error ! +-+-+ /--------+--------\
\-------------/ ! 4 ! ! intrq, reset busy !
\ / \-----------------/
+---+ write sector
! 3 ! sequence
\ /
!
+-----------+----------+
! delay 2 bytes of gap !
+----------------------+
! set drq !
+----------------------+
! delay 9 bytes of gap !
+-----------+----------+
!
+----+----+
/ has DR \
! been loaded !
\ (DRQ= 0) /
+----+----+
!yes
+-----------+----------+
! delay 1 byte of gap !--------------+
+-----------+----------+ !
+--+--+
no / is \
+------<-------------! notDDEN !
! \ = 0 ? /
! +--+--+
+-------+-------+ !yes
! turn on wg & ! +--------+--------+
! write 6x 00 ! ! delay 11 bytes !
+-------+-------+ +--------+--------+
! !
+---------+---------+ +-------+-------+
! write data AM !--<----! turn on wg & !
! according to a0 ! ! write 12x 00 !
! bit of write cmd ! +---------------+
+---------+---------+
!
+---------->-----+
! !
! +---------+---------+
! ! DR to DSR,set DRQ !
! +-------------------+
! ! write byte to DSR !
! +---------+---------+
! !
! +---+---+
! / has \ no +---------------+
! ! dr been !--->-! set data lost !
! ! loaded ! ! write 1x 00 !
! \ (drq= 0)/ +-------+-------+
! +---+---+ !
! !yes !
! +--------<----------+
! !
! +----+----+
! no / have all \ yes
+---<-----! bytes been !----->--+
\ assembled / !
+----+----+ +------+------+
! write crc !
+-------------+
! write 1x FF !
+-------------+
! turn off wg !
+------+------+
!
+-+-+
! 5 !
\ /
TYPE 3
!
+---<--------+
! !
+--+--+ !
/is this\ no !
! a write !---->--+
\ track /
+--+--+
!yes
+-----------+-----------+
! set busy, reset drq, !
! lost data (bit 4,5) !
+-----------+-----------+
!
+-+-+
/ is \ no
! h = 1 !------->-----+
\ ? / !
+-+-+ !
!yes !
+--------+--------+ !
! set MO, wait 6 ! !
! index pulses ! !
+--------+--------+ !
! !
+-----<-----------+
!
+-+-+
/ is \ no
! E = 1 !--------->------+
\ ? / !
+-+-+ !
!yes !
+----<-------+ !
! ! !
+---+---+ ! !
/ has \ no ! !
! 30msec !--->--+ !
\ expired / !
+---+---+ !
!yes !
+-------<------------+
! +------->--+----<-------+
+---+---+ ! ! !
/ is \ yes /-------------\ ! +-----+----+ !
! notWPRT !----->--! intrq, reset ! ! / has \ no !
\ = 0 ? / ! busy set wprt ! ! ! index pulse !--->-+
+---+---+ \-------------/ ! \ occurred /
!no ! +----+----+ +---+
+-------+-------+ ! !yes ! A !
! set DRQ ! ! ! \ /
+-------+-------+ ! ! !
! ! !---<--------+
+-------+-------+ ! !
! delay 3 byte ! ! +-----+-----+
! times ! ! ! DR to DSR !
+-------+-------+ ! +-----+-----+
! ! !
+--+--+ /----------------\ ! +-----+-----+
/ has \ no ! intrq, set lost ! ! ! set DRQ !
! DRQ been!--->-! data, reset busy ! ! +-----+-----+
\service/ \----------------/ ! !
+--+--+ ! +-+-+
!yes ! ! B !
+---------------------->---------+ \ /
+---+
! B !
\ /
!
+--+--+
no (FM) / is \ yes (MFM)
+-------<-------------! notDDEN !---------------->--------+
! \ = 0 ? / !
! +--+--+ !
+--+--+ +--+--+
/ is \ yes +-----------+ +---------------+ yes / is \
! DSR=$F7 !--->-! wt 2x CRC !->-+-<-! wt A1 in MFM, !-<---! DSR=$F5 !
\ ? / ! CLK = FF ! ! ! missing CLK, ! \ ? /
+--+--+ +-----------+ ! ! init CRC ! +--+--+
!no ! +---------------+ !no
+--+--+ ! +--+--+
/ is \ yes +-----------+ ! +---------------+ yes / is \
! DSR=$FC !--->-! write FC, !->-+-<-! wt C2 in MFM, !-<---! DSR=$F6 !
\ / ! CLK = F7 ! ! ! with ! \ ? /
+--+--+ +-----------+ ! ! missing CLK ! +--+--+
!no ! +---------------+ !no
+--+--+ +-----------+ ! +--+--+
/is DSR \ yes ! wt FD,FE, ! ! +---------------+ yes / is \
! FD,FE or!--->-! F8-FB,CLK !->-+-<-! generate !-<---! DSR=$F7 !
\ F8-FB / !=C7,initCRC! ! ! 2 bytes CRC ! \ /
+--+--+ +-----------+ ! +---------------+ +--+--+
!no ! !no
+----+----+ ! +----+----+
! wt DSR, !------------->-------+----<--------------------! wt DSR !
! CLK=$FF ! ! ! in MFM !
+---------+ +----<--------------+ +---------+
! !
+---+---+ !
/------------\ yes / phys \ !
! intrq, reset !-<---! index mark! !
! busy flag ! \ ? / !
\------------/ +---+---+ !
! !
+---+---+ !
yes / has DSR \ no +-------+-------+
+---<-------! been !--->-! wt 1x 00 !
! \ loaded ?/ ! set data lost !
+-+-+ +-------+ +---------------+
! A !
\ /
Programming information from the data sheets for the Western
Digital 1770-00 and 1772-00 floppy disk drive controllers. David
Gahris, dgahris@eece.maine.edu, typed and edited this on 10 Mar 1995.
Unless I note otherwise, this file applies to both the 1770-00 and
the 1772-00, and I do not deal with other chips in the 1770 family,
such as the 1773-00 or the 1770-02. I call the 1770 and the 1772
collectively the 177x. Except as noted, "clock cycles" are
CPU clock cycles at exactly 1 MHz.
OUTLINE OF CONTENTS:
The names are self-explanatory. All registers are 8 bits wide.
After the CPU writes to any register, it cannot read that register for
16 cycles.
r0 (write) - Command Register - When the 177x is busy, it ignores
CPU writes to this register UNLESS the new command is a force
interrupt.
r0 (read) - Status Register - The value in this register depends
on the previous 177x command. If the 177x receives a Force Interrupt
command while it is executing another command, the FDDC will clear the
Busy bit (Status bit 0: see later in this paragraph), and leave all
other Status bits unchanged. If the 177x receives a Force Interrupt
command while it is not executing a command, the 177x will update the
entire Status Register as though it had just executed a Type I
command. (For an explanation of Type I, Type II, Type III, and Type IV
commands, see the section on commands.) When the CPU is connected
(directly or indirectly) to the 177x's interrupt output, it is a bad
idea to check the Busy bit because a CPU read of the Status Register
clears the 177x's interrupt output. After the CPU writes to the
Command Register, it should not attempt to read the Busy bit for 24
cycles. The CPU should not follow a Command Register write with a read
of Status bits 1-7 until 32 clock cycles have elapsed.
Bits:
Bit 6 - Write Protect. This bit is not used during reads. During
writes, this bit is high when the disk is write protected.
Bit 5 - Spin-up / Record Type. For Type I commands, this bit is
low during the 6-revolution motor spin-up time. This bit is high after
spin-up. For Type II and Type III commands, Bit 5 low indicates a
normal data mark. Bit 5 high indicates a deleted data mark.
Bit 4 - Record Not Found. This bit is set if the 177x cannot find
the track, sector, or side which the CPU requested. Otherwise, this
bit is clear.
Bit 3 - CRC Error. This bit is high if a sector CRC on disk does
not match the CRC which the 177x computed from the data. The CRC
polynomial is x^16+x^12+x^5+1. If the stored CRC matches the newly
calculated CRC, the CRC Error bit is low. If this bit and the Record
Not Found bit are set, the error was in an ID field. If this bit is
set but Record Not Found is clear, the error was in a data field.
Bit 2 - Track Zero / Lost Data. After Type I commands, this bit is
0 if the mechanism is at track zero. This bit is 1 if the head is not
at track zero. After Type II or III commands, this bit is 1 if the CPU
did not respond to Data Request (Status bit 1) in time for the 177x to
maintain a continuous data flow. This bit is 0 if the CPU responded
promptly to Data Request.
Bit 1 - Index / Data Request. On Type I commands, this bit is high
during the index pulse that occurs once per disk rotation. This bit is
low at all times other than the index pulse. For Type II and III
commands, Bit 1 high signals the CPU to handle the data register in
order to maintain a continuous flow of data. Bit 1 is high when the
data register is full during a read or when the data register is empty
during a write. "Worst case service time" for Data Request
is 23.5 cycles.
Bit 0 - Busy. This bit is 1 when the 177x is busy. This bit is 0
when the 177x is free for CPU commands.
r1 (r/w) - Track Register - The outermost track on the disk is
numbered 0. During disk reading, writing, and verifying, the 177x
compares the Track Register to the track number in the sector ID
field. When the 177x is busy, it ignores CPU writes to this register.
The highest legal track number is 240.
r2 (r/w) - Sector Register - During disk reading and writing, the
177x compares the Sector Register to the sector number in the sector
ID field. When the 177x is busy, it ignores CPU writes to this
register. Valid sector numbers range from 1 to 240, inclusive.
r3 (r/w) - Data Register
COMMANDS:
The 177x accepts 11 commands. Western Digital divides these
commands into four categories, labeled I,II, III, and IV.
Type I commands are Restore, Seek, Step, Step In, and Step Out.
Command Bit 7 B6 B5 B4 B3 B2 B1 Bit 0 -------- ----- -- -- -- -- -- -- ----- Restore 0 0 0 0 h V r1 r0 Seek 0 0 0 1 h V r1 r0 Step 0 0 1 u h V r1 r0 Step in 0 1 0 u h V r1 r0 Step out 0 1 1 u h V r1 r0
Flags:
u (Update Track Register) - If this flag is set, the 177x will
update the track register after executing the command. If this flag is
cleared, the 177x will not update the track register.
h (Motor On) - If the value of this bit is 1, the controller will
disable the motor spin-up sequence. Otherwise, if the motor is off
when the chip receives a command, the chip will turn the motor on and
wait 6 revolutions before executing the command. At 300 RPM, the
6-revolution wait guarantees a one-second start time. If the 177x is
idle for 9 consecutive disk revolutions, it turns off the drive motor.
If the 177x receives a command while the motor is on, the controller
executes the command immediately.
V (Verify) - If this flag is set, the head settles after command
execution. The settling time is 15 000 cycles for the 1772 and 30 000
cycles for the 1770. The FDDC will then verify the track position of
the head. The 177x reads the first ID field it finds and compares the
track number in that ID field against the Track Register. If the track
numbers match but the ID field CRC is invalid, the 177x sets the CRC
Error bit in the status register and reads the next ID field. If the
177x does not find a sector with valid track number AND valid CRC
within 5 disk rotations, the chip sets the Seek Error bit in the
status register.
r1 r0 1770 1772 -- -- ---- ---- 0 0 6000 CPU clock cycles 6000 cycles 0 1 12000 cycles 12000 cycles 1 0 20 000 cycles 2000 cycles 1 1 30 000 cycles 3000 cycles
Restore:
Step out:
Type II commands are Read Sector and Write Sector.
Command Bit 7 B6 B5 B4 B3 B2 B1 Bit 0 ------------ ----- -- -- -- -- -- -- ----- Read Sector 1 0 0 m h E 0 0 Write Sector 1 0 1 m h E P a0
m (Multiple Sectors) - If this bit = 0, the 177x reads or writes
("accesses") only one sector. If this bit = 1, the 177x
sequentially accesses sectors up to and including the last sector on
the track. A multiple-sector command will end prematurely when the CPU
loads a Force Interrupt command into the Command Register.
h (Motor On) - If the value of this bit is 1, the controller will
disable the motor spin-up sequence. Otherwise, if the motor is off
when the chip receives a command, the chip will turn the motor on and
wait 6 revolutions before executing the command. At 300 RPM, the
6-revolution wait guarantees a one- second start time. If the 177x is
idle for 9 consecutive disk revolutions, it turns off the drive motor.
If the 177x receives a command while the motor is on, the controller
executes the command immediately.
E (Settling Delay) - If this flag is set, the head settles before
command execution. The settling time is 15 000 cycles for the 1772 and
30 000 cycles for the 1770.
P (Write Precompensation) - On the 1770-02 and 1772-00, a 0 value
in this bit enables automatic write precompensation. The FDDC delays
or advances the write bit stream by one-eighth of a cycle according to
the following table.
Previous Current bit Next bit bits sent sending to be sent Precompensation --------- ----------- ---------- --------------- x 1 1 0 Early x 0 1 1 Late 0 0 0 1 Early 1 0 0 0 Late
Programmers typically enable precompensation on the innermost
tracks, where bit shifts usually occur and bit density is maximal. A 1
value for this flag disables write precompensation.
a0 (Data Address Mark) - If this bit is 0, the 177x will write a
normal data mark. If this bit is 1, the 177x will write a deleted data
mark.
Command Bit 7 B6 B5 B4 B3 B2 B1 Bit 0 ------------ ----- -- -- -- -- -- -- ----- Read Address 1 1 0 0 h E 0 0 Read Track 1 1 1 0 h E 0 0 Write Track 1 1 1 1 h E P 0
h (Motor On) - If the value of this bit is 1, the controller will
disable the motor spin-up sequence. Otherwise, if the motor is off
when the chip receives a command, the chip will turn the motor on and
wait 6 revolutions before executing the command. At 300 RPM, the
6-revolution wait guarantees a one- second start time. If the 177x is
idle for 9 consecutive disk revolutions, it turns off the drive motor.
If the 177x receives a command while the motor is on, the controller
executes the command immediately.
E (Settling Delay) - If this flag is set, the head settles before
command execution. The settling time is 15 000 cycles for the 1772 and
30 000 cycles for the 1770.
P (Write Precompensation) - On the 1770-02 and 1772-00, a 0 value
in this bit enables automatic write precompensation. The FDDC delays
or advances the write bit stream by one-eighth of a cycle according to
the following table.
Previous Current bit Next bit bits sent sending to be sent Precompensation --------- ----------- ---------- --------------- x 1 1 0 Early x 0 1 1 Late 0 0 0 1 Early 1 0 0 0 Late
Programmers typically enable precompensation on the innermost
tracks, where bit shifts usually occur and bit density is maximal. A 1
value for this flag disables write precompensation.
Byte # Meaning | Sector length code Sector length ------ ------------------ | ------------------ ------------- 1 Track | 0 128 2 Side | 1 256 3 Sector | 2 512 4 Sector length code | 3 1024 5 CRC byte 1 | 6 CRC byte 2 |
[Transcriber's Note: | is the vertical bar character.]
The 177x copies the track address into the Sector Register. The
chip sets the CRC Error bit in the status register if the CRC is
invalid.
Read Track:
Force Interrupt:
INTERRUPTS:
The 177x interrupts the CPU: *each time it finishes a command, *if
a Force Interrupt condition is true, or *if the FDDC tries to write to
a write-protected disk. The 177x's interrupt output pin resets when
the CPU reads the status register or writes to the command register,
except after a Force Interrupt (immediate) command. See the section on
the Force Interrupt command.
DISK FORMATTING:
The 177x formats disks according to the IBM 3740 or System/34
standard. See the Write Track command for the CPU formatting method.
The recommended physical format for 256-byte sectors is as follows.
Number of Bytes Value of Byte Comments
--------------- ------------- --------
60 $4e Gap 1 and Gap 3. Start and end of index
pulse.
12 $00 Gap 3. Start of bytes repeated for each
sector.
3 $a1 Gap 3. Start of ID field. See section
on Write Track command.
1 $fe ID address mark
1 track # $00 through $4c (0 through 76)
1 side # 0 or 1
1 sector # $01 through $10 (1 through 16)
1 length code See section on Read Address command.
2 CRC End of ID field. See section on Write
Track command.
22 $4e Gap 2.
12 $00 Gap 2. During Write Sector commands the
drive starts writing at the start
of this.
3 $a1 Gap 2. Start of data field. See
section on Write Track command.
1 $fb data address mark
256 data Values $f5, $f6, and $f7 invalid. See
section on Write Track command. IBM
uses $e5.
2 CRC End of data field. See section on Write
Track command.
24 $4e Gap 4. End of bytes repeated for each
sector. During Write Sector
commands the drive stops writing shortly
after the beginning of this.
668 $4e Continue writing until the 177x
generates an interrupt. The listed byte
count is approximate.
The 177x does not require an Index Address Mark.
MISCELLANEOUS:
The chip steps the drive head in the same direction it last
stepped unless the command changes the direction. Each step pulse
takes 4 cycles. The 177x begins outputting a direction signal to the
drive 24 cycles before the first stepping pulse. The 177x is designed
for a head data rate of 250 kilobits per second. If the CPU does not
give the 177x a byte by the time the 177x needs to write to the disk,
the 177x writes a zero byte instead. The minimum cycle time of the raw
head data input is 3 CPU clock cycles. The head data output has a
cycle time of 4, 6, or 8 CPU clock cycles. The head data output pulse
width is .82 clock cycles for an early bit, .69 cycles for a normal
bit, and .57 cycles for a late bit. See the Commands section for
information on write precompensation. The 1772-02 is 100%
software-compatible with the 1772-00. During DMA between the 177x and
CPU RAM, the DRQ (Data Request) pin of the 177x controls data
transfer. The DRQ pin is high when the Data Request bit in the Status
Register is high, and the DRQ pin is low when the Data Request bit is
low.
Copyright © Robert Schaffner (doit@doitarchive.de) Letzte Aktualisierung am 23. Mai 2004 |
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