15.6.5 Cardridge Port Interface

Cartridge Port Interface

April 14, 1987

Abstract

The Atari ST's 128 Kbyte read-only cartridge port can be transformed into a 64 Kbyte read/write port by using this circuit. Writing to this port is slower than reading it by a factor of two, approximately. It can be written to at a speed of 76 Kilowords per second.

This interface can be built by using only three chips, two AS-TTLs and a PAL - a total parts cost of less than $15.

How It works

1. Background Information

The ST brings out 15 address lines (A1-A15), 16 data lines (d0-D15) /LDS, [*] /UDS, /AS, /ROM4 and /ROM3.

Of these signals, /UDS, /LDS, and /AS have the same meaning as they do for a 68000 CPU. A1-A15 are the least significant 15 address lines. D0-D15 are connected internally to the ST's data-bus. /ROM3 and /ROM4 are generated by the MMU, and are output signals, which tell the external hardware which of the two banks is being addressed. /ROM4 is activated when the 68000 tries to read address 0xfa0000-0xfaffff. /ROM3 is activated when the 68000 tries to read address 0xfb0000-0xfbffff (note that the names of these signals are counterintuitive; ie. they have been correctly written above).

2. Caveats

Any and all hardware connected to this modified port must be fast - fast enough to run with no wait-states and fast enough to tolerate the decoding delays introduced by this circuit. I've used 200ns static RAM chips without any trouble.

It is advisable to use /ROM4 to time any external hardware you build (in preference to /AS), since /ROM4 contains the necessary delay to ensure the addresses are stable when it is activated. (At least this is what I assumed, and it worked.)

The data for write operations is produced by the two AS-TTL latches[*] used in the circuit (see below.)

[*] A preceeding slash indicates an active-low signal

3. Operating Principle

3.1.

The PAL contains an asynchronous finite state machine. When the upper bank (address 0xfbxxxx) is read, the PAL manufactures an A0 (based on the state of /UDS and /LDS) and supplies this to U1. At the end of the read cycle, U1 and U2 are clocked to latch the least significant 16 address bits into the PAL.
 

3.2.

Subsequently, when the lower bank is read (address 0xfaxxxx), the latched address (which was latched in step 1) is supplied as data and /PWE (the write-enable signal) is activated (it goes low). /ROM4 active should tell the external hardware that it is being addressed and /PWE active should tell it that this is a write-cycle. As an interesting side-effect of this design, the data word written out is read back by the 68000 (you can use this fact to debug the interface!).
 

3.3.

Reads to the upper bank will return garbage, unless some ROM is present there. Multiple successive reads to this bank will not be harmful (ie. they will not confuse the state-machine) and the latest adress will be latched preparation for a read to the lower bank.
 
Note that if you put RAM in the upper-bank, you will not be able to write to it. Connecting the /PWE line to such RAM will have no effect Putting a ROM in this address space should not create any problems (although I haven't tried this).
 

Example:

 
To write data 0xcd01 to address 0x3bc0 in the lower bank, the following steps are performed.

 
step1. read byte at address 0xfbcd01 (0xfb0000+data)
step2. read word to address 0xfa3bc0 (0xfa0000+addr)

 
[*] I used AS374s, you can use AS or FAST. High speed chips are necessary so that delays from /OE (latch output-enable) to valid data are not critical. You could possibly get away with ALSTTL, but I haven't tried this.

 

Construction

The schematic should help in this department. Constructing this gadget is easy and cheap. The hardest part might be trying to find a connector for this port. You can get one from:

Douglas Electronics,
718 Marina Blvd.,
SAN LEANDRO, Calif. 94577

1-415-483-8770

(part number 33-DE-40. $10.00 per piece)

[*] Another problem you might face is getting the PAL programmed. If you don't know of a way to get the PAL programmed, you could use discrete logic chips to build the state machine.

4. Building it

The pin-outs given in the User's guide are CORRECT. The pin-outs given in the "Internals" book are WRONG. Follow the schematic. You can get the pinouts for the '374s from an ASTTL or FAST databook. The PAL16L8's pinouts are given below.

[*] You guessed it - I'm not connected with D.E. although I and a number of others have purchased these connectors from them.

PAL Pinouts in the external "Program" Folder

Legend:

A preceding slash implies an active-low signal.
NC implies no-contact (nothing should be connected to these pins.)
(i) indicates that the signal is an input.
(o) indicates that the signal is an output.
(A) implies that the signal comes from/goes to the Atari cart. port.
(u1) implies that the signal goes to U1, the least-significant latch.
(u2) implies that the signal goes to U2, the most-significant latch.
(ex) implies that the signal goes to any external hardware connected, such as a ram-disk.

Note that the line called "help" is shown as "NC" since it is to be left unconnected.

Anees Munshi.
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